[llvm] [RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (PR #92768)

[Craig Topper via llvm-commits]

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@@ -1677,8 +1677,9 @@ let Predicates = [HasVInstructions] in {
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>;
 def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
-                      SchedBinaryMC<"WriteVRGatherVV", "ReadVRGatherVV_data",
-                                    "ReadVRGatherVV_index">;
+                      SchedBinaryMC<"WriteVRGatherVVEEW",
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topperc wrote:

I'm unsure what EEW is meant to convey here. Every operand of every vector instruction has an EEW. For vrgather.vv, for all operands EEW=SEW. For vrgatherei16.vv, the index operand has EEW=16 and the data and index operands have EEW=SEW.

https://github.com/llvm/llvm-project/pull/92768