[llvm] [AMDGPU] Add IR LiveReg type-based optimization (PR #66838)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

> How does this compare to the usage of
> 
> https://github.com/llvm/llvm-project/blob/3684a38d33d7643fe8c3a870006efa8677ac37f8/llvm/include/llvm/CodeGen/TargetLowering.h#L2869
> 
> in generic CodeGenPrepare?

Interesting -- I did not see that, thanks.

That feature does have the same structure as the feature in this PR, but it seems for a different purpose: to help fold away bitcasts. It will insert bitcasts if it finds that the bitcasts defining incoming values and bitcast uses of the PHI are all the same type. The target hook is invoked in special cases: when there are no bitcast def/uses, or when the bitcasts are def by a load (for bitcast def) / used by a store (for bitcast use of PHI).

It is mainly due to this special condition entry that the hook will not work for the feature in this PR. Not only that special condition, but the generic codegenprepare optimizePhiType is disabled for vector types. Of course we could remove the conditions to the target hook, but this feels like misusing the hook since the features are conceptually different and we will have a phase ordering problem (code sinking will fold the newly inserted casts).

https://github.com/llvm/llvm-project/pull/66838