[llvm] 02f1a99 - [DivRemPairs] Pre-commit tests for PR #92627 (#92628)
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Mon May 20 08:28:26 PDT 2024
Author: Krzysztof Drewniak
Date: 2024-05-20T10:28:20-05:00
New Revision: 02f1a992035f40b49435f0e7f358badd152d9dc2
URL: https://github.com/llvm/llvm-project/commit/02f1a992035f40b49435f0e7f358badd152d9dc2
DIFF: https://github.com/llvm/llvm-project/commit/02f1a992035f40b49435f0e7f358badd152d9dc2.diff
LOG: [DivRemPairs] Pre-commit tests for PR #92627 (#92628)
The tests are added to a new AMDGPU/ subdirectory since I found the
missed optimization while hacking on AMDGPU code. Also, this ensures
that AMDGPU, which uses DivRemPass, is being checked for existing
expected behavior.
Added:
llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
llvm/test/Transforms/DivRemPairs/AMDGPU/lit.local.cfg
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll b/llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
new file mode 100644
index 0000000000000..bd7a20a98539e
--- /dev/null
+++ b/llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=div-rem-pairs -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
+
+define i32 @basic(ptr %p, i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @basic(
+; CHECK-SAME: ptr [[P:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
+; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X_FROZEN]], [[Y_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %div = udiv i32 %x, %y
+ %rem = urem i32 %x, %y
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
+
+define i32 @no_freezes(ptr %p, i32 noundef %x, i32 noundef %y) {
+; CHECK-LABEL: define i32 @no_freezes(
+; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X]], [[Y]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %div = udiv i32 %x, %y
+ %rem = urem i32 %x, %y
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
+
+; FIXME: There should be no need to `freeze` x2 and y2 since they have defined
+; but potentially poison values.
+define i32 @poison_does_not_freeze(ptr %p, i32 noundef %x, i32 noundef %y) {
+; CHECK-LABEL: define i32 @poison_does_not_freeze(
+; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw i32 [[X]], 5
+; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
+; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze i32 [[X2]]
+; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X2_FROZEN]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X2_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %x2 = shl nuw nsw i32 %x, 5
+ %y2 = add nuw nsw i32 %y, 1
+ %div = udiv i32 %x2, %y2
+ %rem = urem i32 %x2, %y2
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
+
+define i32 @poison_does_not_freeze_signed(ptr %p, i32 noundef %x, i32 noundef %y) {
+; CHECK-LABEL: define i32 @poison_does_not_freeze_signed(
+; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw i32 [[X]], 5
+; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
+; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze i32 [[X2]]
+; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X2_FROZEN]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X2_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %x2 = shl nuw nsw i32 %x, 5
+ %y2 = add nuw nsw i32 %y, 1
+ %div = sdiv i32 %x2, %y2
+ %rem = srem i32 %x2, %y2
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
+
+define <4 x i8> @poison_does_not_freeze_vector(ptr %p, <4 x i8> noundef %x, <4 x i8> noundef %y) {
+; CHECK-LABEL: define <4 x i8> @poison_does_not_freeze_vector(
+; CHECK-SAME: ptr [[P:%.*]], <4 x i8> noundef [[X:%.*]], <4 x i8> noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[X2:%.*]] = shl nuw nsw <4 x i8> [[X]], <i8 5, i8 5, i8 5, i8 5>
+; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw <4 x i8> [[Y]], <i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT: [[X2_FROZEN:%.*]] = freeze <4 x i8> [[X2]]
+; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze <4 x i8> [[Y2]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv <4 x i8> [[X2_FROZEN]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[DIV]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub <4 x i8> [[X2_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store <4 x i8> [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret <4 x i8> [[REM_DECOMPOSED]]
+;
+ %x2 = shl nuw nsw <4 x i8> %x, <i8 5, i8 5, i8 5, i8 5>
+ %y2 = add nuw nsw <4 x i8> %y, <i8 1, i8 1, i8 1, i8 1>
+ %div = udiv <4 x i8> %x2, %y2
+ %rem = urem <4 x i8> %x2, %y2
+ store <4 x i8> %div, ptr %p, align 4
+ ret <4 x i8> %rem
+}
+
+define i32 @explicit_poison_does_not_freeze(ptr %p, i32 noundef %y) {
+; CHECK-LABEL: define i32 @explicit_poison_does_not_freeze(
+; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[X:%.*]] = add i32 poison, 1
+; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
+; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
+; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[X_FROZEN]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %x = add i32 poison, 1
+ %y2 = add nuw nsw i32 %y, 1
+ %div = udiv i32 %x, %y2
+ %rem = urem i32 %x, %y2
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
+
+define i32 @explicit_poison_does_not_freeze_signed(ptr %p, i32 noundef %y) {
+; CHECK-LABEL: define i32 @explicit_poison_does_not_freeze_signed(
+; CHECK-SAME: ptr [[P:%.*]], i32 noundef [[Y:%.*]]) {
+; CHECK-NEXT: [[X:%.*]] = add i32 poison, 1
+; CHECK-NEXT: [[Y2:%.*]] = add nuw nsw i32 [[Y]], 1
+; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X]]
+; CHECK-NEXT: [[Y2_FROZEN:%.*]] = freeze i32 [[Y2]]
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X_FROZEN]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[Y2_FROZEN]]
+; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P]], align 4
+; CHECK-NEXT: ret i32 [[REM_DECOMPOSED]]
+;
+ %x = add i32 poison, 1
+ %y2 = add nuw nsw i32 %y, 1
+ %div = sdiv i32 %x, %y2
+ %rem = srem i32 %x, %y2
+ store i32 %div, ptr %p, align 4
+ ret i32 %rem
+}
diff --git a/llvm/test/Transforms/DivRemPairs/AMDGPU/lit.local.cfg b/llvm/test/Transforms/DivRemPairs/AMDGPU/lit.local.cfg
new file mode 100644
index 0000000000000..7c492428aec76
--- /dev/null
+++ b/llvm/test/Transforms/DivRemPairs/AMDGPU/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "AMDGPU" in config.root.targets:
+ config.unsupported = True
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