[llvm] [AMDGPU] Change control flow intrinsic lowering making the wave to re… (PR #86805)

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``````````bash
git-clang-format --diff 82c5d350d200ccc5365d40eac187b9ec967af727 a96acb5340f4c6d2ef1884eb2ce374b2a28081db -- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
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diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
index 68d81a6ffa..8e909e5afb 100644
--- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
@@ -13,9 +13,9 @@
 
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
+#include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/UniformityAnalysis.h"
-#include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Constants.h"
@@ -142,7 +142,8 @@ void SIAnnotateControlFlow::initialize(Module &M, const GCNSubtarget &ST) {
   IfBreak = Intrinsic::getDeclaration(&M, Intrinsic::amdgcn_if_break,
                                       { IntMask });
   Loop = Intrinsic::getDeclaration(&M, Intrinsic::amdgcn_loop, { IntMask });
-  WaveReconverge = Intrinsic::getDeclaration(&M, Intrinsic::amdgcn_wave_reconverge, { IntMask });
+  WaveReconverge = Intrinsic::getDeclaration(
+      &M, Intrinsic::amdgcn_wave_reconverge, {IntMask});
 }
 
 /// Is the branch condition uniform or did the StructurizeCFG pass
@@ -331,14 +332,14 @@ bool SIAnnotateControlFlow::tryWaveReconverge(BasicBlock *BB) {
     for (auto Succ : Term->successors()) {
       if (isTopOfStack(Succ)) {
         // Just split to make a room for further WAVE_RECONVERGE insertion
-        SmallVector<BasicBlock*, 2> Preds;
+        SmallVector<BasicBlock *, 2> Preds;
         for (auto P : predecessors(Succ)) {
           if (DT->dominates(BB, P))
             Preds.push_back(P);
         }
         DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager);
-        SplitBlockPredecessors(Succ, Preds, ".reconverge", &DTU, LI,
-                                            nullptr, false);
+        SplitBlockPredecessors(Succ, Preds, ".reconverge", &DTU, LI, nullptr,
+                               false);
       }
     }
   }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ea1e7c782e..b3984d4124 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9941,8 +9941,9 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
     return SDValue(Load, 0);
   }
   case Intrinsic::amdgcn_wave_reconverge:
-    return SDValue(DAG.getMachineNode(AMDGPU::SI_WAVE_RECONVERGE, DL, MVT::Other,
-                                      Op->getOperand(2), Chain), 0);
+    return SDValue(DAG.getMachineNode(AMDGPU::SI_WAVE_RECONVERGE, DL,
+                                      MVT::Other, Op->getOperand(2), Chain),
+                   0);
   case Intrinsic::amdgcn_s_barrier_init:
   case Intrinsic::amdgcn_s_barrier_join:
   case Intrinsic::amdgcn_s_wakeup_barrier: {
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 15f1c776cd..216cf963ec 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -214,9 +214,8 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
   // Get rid of the garbage bits in the Cond register which might be coming from
   // the bitwise arithmetic when one of the expression operands is coming from
   // the outer scope and hence having extra bits set.
-  MachineInstr *CondFiltered = BuildMI(MBB, I, DL, TII->get(AndOpc), MaskThen)
-                                   .add(Cond)
-                                   .addReg(Exec);
+  MachineInstr *CondFiltered =
+      BuildMI(MBB, I, DL, TII->get(AndOpc), MaskThen).add(Cond).addReg(Exec);
   if (LV)
     LV->replaceKillInstruction(CondReg, MI, *CondFiltered);
 
@@ -304,9 +303,9 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) {
                                  .addReg(MaskLoop)
                                  .addImm(TestMask);
 
-  MachineInstr *SetExec= BuildMI(MBB, &MI, DL, TII->get(Select), Exec)
-                                     .addReg(MaskLoop)
-                                     .addReg(Cond);
+  MachineInstr *SetExec = BuildMI(MBB, &MI, DL, TII->get(Select), Exec)
+                              .addReg(MaskLoop)
+                              .addReg(Cond);
 
   if (LV)
     LV->replaceKillInstruction(MI.getOperand(0).getReg(), MI, *SetExec);
@@ -371,7 +370,7 @@ void SILowerControlFlow::emitWaveDiverge(MachineInstr &MI,
     MachineInstr *CopyExec =
         BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DisableLanesMask)
             .addReg(Exec);
-    if(LIS)
+    if (LIS)
       LIS->InsertMachineInstrInMaps(*CopyExec);
   }
   Register TestResultReg = MRI->createVirtualRegister(BoolRC);
@@ -385,7 +384,7 @@ void SILowerControlFlow::emitWaveDiverge(MachineInstr &MI,
 
   MachineBasicBlock *FlowBB = MI.getOperand(2).getMBB();
   MachineBasicBlock *TargetBB = nullptr;
-    // determine target BBs
+  // determine target BBs
   I = skipToUncondBrOrEnd(MBB, I);
   if (I != MBB.end()) {
     // skipToUncondBrOrEnd returns either unconditional branch or end()
@@ -416,7 +415,7 @@ void SILowerControlFlow::emitWaveDiverge(MachineInstr &MI,
     return;
   }
 
-    LIS->InsertMachineInstrInMaps(*IfZeroMask);
+  LIS->InsertMachineInstrInMaps(*IfZeroMask);
   LIS->ReplaceMachineInstrInMaps(MI, *SetExecForSucc);
 
   RecomputeRegs.insert(MI.getOperand(0).getReg());
@@ -429,7 +428,7 @@ void SILowerControlFlow::emitWaveDiverge(MachineInstr &MI,
   LIS->removeAllRegUnitsForPhysReg(Exec);
 }
 
-void SILowerControlFlow::emitWaveReconverge(MachineInstr &MI) { 
+void SILowerControlFlow::emitWaveReconverge(MachineInstr &MI) {
 
   MachineBasicBlock &BB = *MI.getParent();
   Register Mask = MI.getOperand(0).getReg();

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https://github.com/llvm/llvm-project/pull/86805