[llvm] [GISel][RISCV] Add legalizer & selector support for G_FREEZE. (PR #92744)
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Mon May 20 05:47:26 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-risc-v
Author: Yingwei Zheng (dtcxzyw)
<details>
<summary>Changes</summary>
This patch adds support for G_FREEZE on riscv. It will be selected into a copy instruction.
The ll test is copied from the AArch64 patch: https://github.com/llvm/llvm-project/commit/665da596854bf07ee25f368855156dde43845013.
---
Full diff: https://github.com/llvm/llvm-project/pull/92744.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+1)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+2-1)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll (+164)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir (+62)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir (+96)
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 791d364655e56..da8daa573b89b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -558,6 +558,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_FREEZE:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT: {
Register DstReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index adc68e9ee4a89..c73fe2c6cecbe 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -227,7 +227,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
ConstantActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen);
// TODO: transform illegal vector types into legal vector type
- getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
+ getActionDefinitionsBuilder(
+ {G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER, G_FREEZE})
.legalFor({s32, sXLen, p0})
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
new file mode 100644
index 0000000000000..ebf4a7958e6a9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+
+%struct.T = type { i32, i32 }
+
+define i32 @freeze_int() {
+; RV32-LABEL: freeze_int:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: call __mulsi3
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_int:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: call __muldi3
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %y1 = freeze i32 undef
+ %t1 = mul i32 %y1, %y1
+ ret i32 %t1
+}
+
+define i5 @freeze_int2() {
+; RV32-LABEL: freeze_int2:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: call __mulsi3
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_int2:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: call __muldi3
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+ %y1 = freeze i5 undef
+ %t1 = mul i5 %y1, %y1
+ ret i5 %t1
+}
+
+define float @freeze_float() {
+; CHECK-LABEL: freeze_float:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fadd.s fa0, fa5, fa5
+; CHECK-NEXT: ret
+ %y1 = freeze float undef
+ %t1 = fadd float %y1, %y1
+ ret float %t1
+}
+
+; TODO: Support vector return values.
+; define <2 x i32> @freeze_ivec() {
+; %y1 = freeze <2 x i32> undef
+; %t1 = add <2 x i32> %y1, %y1
+; ret <2 x i32> %t1
+; }
+
+define ptr @freeze_ptr() {
+; CHECK-LABEL: freeze_ptr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 4
+; CHECK-NEXT: ret
+ %y1 = freeze ptr undef
+ %t1 = getelementptr i8, ptr %y1, i64 4
+ ret ptr %t1
+}
+
+define i32 @freeze_struct() {
+; RV32-LABEL: freeze_struct:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_struct:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze %struct.T undef
+ %v1 = extractvalue %struct.T %y1, 0
+ %v2 = extractvalue %struct.T %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct() {
+; RV32-LABEL: freeze_anonstruct:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct:
+; RV64: # %bb.0:
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze {i32, i32} undef
+ %v1 = extractvalue {i32, i32} %y1, 0
+ %v2 = extractvalue {i32, i32} %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct2() {
+; RV32-LABEL: freeze_anonstruct2:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a0, 16
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a0
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct2:
+; RV64: # %bb.0:
+; RV64-NEXT: lui a0, 16
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a0
+; RV64-NEXT: addw a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze {i32, i16} undef
+ %v1 = extractvalue {i32, i16} %y1, 0
+ %v2 = extractvalue {i32, i16} %y1, 1
+ %z2 = zext i16 %v2 to i32
+ %t1 = add i32 %v1, %z2
+ ret i32 %t1
+}
+
+define i64 @freeze_array() {
+; RV32-LABEL: freeze_array:
+; RV32: # %bb.0:
+; RV32-NEXT: add a0, a0, a0
+; RV32-NEXT: sltu a1, a0, a0
+; RV32-NEXT: add a2, a0, a0
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_array:
+; RV64: # %bb.0:
+; RV64-NEXT: add a0, a0, a0
+; RV64-NEXT: ret
+ %y1 = freeze [2 x i64] undef
+ %v1 = extractvalue [2 x i64] %y1, 0
+ %v2 = extractvalue [2 x i64] %y1, 1
+ %t1 = add i64 %v1, %v2
+ ret i64 %t1
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
new file mode 100644
index 0000000000000..4217910dc506f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv32 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: freeze_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = G_FREEZE %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_f32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = G_FREEZE %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: freeze_nxv2i1
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s1>) = COPY $v8
+ %2:_(<vscale x 2 x s1>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s1>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s32>) = COPY $v8
+ %2:_(<vscale x 2 x s32>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir
new file mode 100644
index 0000000000000..355e225915884
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir
@@ -0,0 +1,96 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv64 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: freeze_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s32) = G_TRUNC %1(s64)
+ %3:_(s32) = G_FREEZE %2
+ %4:_(s64) = G_ANYEXT %3(s32)
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_f32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = G_FREEZE %1
+ $f10_f = COPY %2(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: freeze_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FREEZE]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_FREEZE %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: freeze_nxv2i1
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s1>) = COPY $v8
+ %2:_(<vscale x 2 x s1>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s1>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %1:_(<vscale x 2 x s32>) = COPY $v8
+ %2:_(<vscale x 2 x s32>) = G_FREEZE %1
+ $v8 = COPY %2(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: freeze_nxv2i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: freeze_nxv2i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s64>) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: $v8m2 = COPY [[FREEZE]](<vscale x 2 x s64>)
+ ; CHECK-NEXT: PseudoRET implicit $v8m2
+ %1:_(<vscale x 2 x s64>) = COPY $v8
+ %2:_(<vscale x 2 x s64>) = G_FREEZE %1
+ $v8m2 = COPY %2(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
``````````
</details>
https://github.com/llvm/llvm-project/pull/92744
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