[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

================
@@ -140,8 +140,9 @@ define <4 x i1> @buildvec_mask_v4i1() {
 define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
 ; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
----------------
BeMg wrote:

There are different order of `PseudoVMV_V_X_MF4` and `PseudoVMV_V_I_MF8` between post-ra nad pre-ra in vsetvl 
insertion pass.

```
; before pre-ra vsetvl insertion
    %2:vr = PseudoVMV_V_X_MF4 undef %2, %1, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    %6:vr = PseudoVMV_V_I_MF8 undef %6, 3, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
```

```
; before post-ra vsetvl insertion
    renamable $v0 = PseudoVMV_V_I_MF8 undef renamable $v0, 3, 1, 3 /* e8 */, 0 /* tu, mu */
    renamable $v8 = PseudoVMV_V_X_MF4 undef renamable $v8, %1, 4, 3 /* e8 */, 0 /* tu, mu */
```

> machine scheduler will make them in same order (`VMV_V_I` then `VMV_V_X`). 

For `emitVSETVLIs`, it needs to insert an extra VSETVL with `VMV_V_I` then `VMV_V_X` order. @lukel97, is there a chance to fix this during the `RISCVCoalesceVSETVLI`?

https://github.com/llvm/llvm-project/pull/70549