[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

================
@@ -197,28 +197,51 @@ entry:
 define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data) {
 ; RV64-LABEL: test_compresstore_v256i8:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    vmv1r.v v7, v8
----------------
BeMg wrote:

>From the register allocation process, the main reason for the less optimal regalloc is the register allocator making varying eviction decisions. These decisions differ due to different LiveInterval spill weights (evicting the one with the smaller weight). One factor in the weight calculation is the LiveInterval's size (And it changed between pre-ra and post-ra vsetvl flow).

---
In this testcase `%12` going to evict. 

```
selectOrSplit VRM8:%12 [240e,288r:0) 0 at 240e  weight:4.454343e-03 w=4.454343e-03
```

pre-ra flow choose evict `%2`

```
VR:%2 [48r,336r:0) 0 at 48r  weight:4.404070e-03 w=4.404070e-03
VRM8:%3 [32r,240r:0) 0 at 32r  weight:3.322368e-03 w=3.322368e-03

...

unassigning %2 from $v8: V8
assigning %12 to $v8m8: V8 [240e,288r:0) 0 at 240e V9 [240e,288r:0) 0 at 240e V10 [240e,288r:0) 0 at 240e V11 [240e,288r:0) 0 at 240e V12 [240e,288r:0) 0 at 240e V13 [240e,288r:0) 0 at 240e V14 [240e,288r:0) 0 at 240e V15 [240e,288r:0) 0 at 240e
```

post-ra flow choose evict `%3` because `%2` spill weight is heavy than `%12`. 

```
VR:%2 [48r,256r:0) 0 at 48r  weight:4.983553e-03 w=4.983553e-03
VRM8:%3 [32r,192r:0) 0 at 32r  weight:3.607143e-03 w=3.607143e-03

...

unassigning %3 from $v16m8: V16 V17 V18 V19 V20 V21 V22 V23
assigning %12 to $v16m8: V16 [192e,224r:0) 0 at 192e V17 [192e,224r:0) 0 at 192e V18 [192e,224r:0) 0 at 192e V19 [192e,224r:0) 0 at 192e V20 [192e,224r:0) 0 at 192e V21 [192e,224r:0) 
```

The second round for %3 assign cause the spill code insertion.



https://github.com/llvm/llvm-project/pull/70549