[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu May 16 01:05:06 PDT 2024
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@@ -590,13 +590,12 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB46_2:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: csrr a0, vlenb
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BeMg wrote:
> This delta is interesting and surprising - in a good way.
>
> I hadn't considered that this change would allow reuse of the vlenb CSR read.
I think it is a coincidence that `PseudoReadVLENB` chooses `$x11` as the destination register (`$x10` is still used by vsetvl) during `Prologue/Epilogue Insertion & Frame Finalization`, allowing the `Machine Late Instructions Cleanup Pass` to reuse definitions from predecessors.
https://github.com/llvm/llvm-project/pull/70549
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