[llvm] [RISCV][LSR] Account for temporary register for base addition (PR #92296)

[Alex Bradbury via llvm-commits]

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asb wrote:

Quick comment as I'm about to log off for a bit:
* I _think_ you forgot to delete "; FIXME: RV32 is working as expected, but RV64 doesn't"
* Would this be better as an IR test (`opt -loop-reduced`) in llvm/test/Transforms/LoopStrengthReduce/RISCV, or is there a reason it works better testing the generated instructions rather than the LSR transform directly? (if you'd considered that and opted for this approach I'm not arguing against it - just wanted to check)

https://github.com/llvm/llvm-project/pull/92296