[llvm] [RISCV][LSR] Account for temporary register for base addition (PR #92296)

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git-clang-format --diff 03c53c69a367008da689f0d2940e2197eb4a955c fa434b1d74fed5cda8b8a429c2e96a777125f1bf -- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 6aa3175a1c..449f405e4c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1863,12 +1863,10 @@ bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
   // we need at least one extra temporary register.
   unsigned C1NumRegs = C1.NumRegs + (C1.NumBaseAdds != 0);
   unsigned C2NumRegs = C2.NumRegs + (C2.NumBaseAdds != 0);
-  return std::tie(C1.Insns, C1NumRegs, C1.AddRecCost,
-                  C1.NumIVMuls, C1.NumBaseAdds,
-                  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
-         std::tie(C2.Insns, C2NumRegs, C2.AddRecCost,
-                  C2.NumIVMuls, C2.NumBaseAdds,
-                  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
+  return std::tie(C1.Insns, C1NumRegs, C1.AddRecCost, C1.NumIVMuls,
+                  C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
+         std::tie(C2.Insns, C2NumRegs, C2.AddRecCost, C2.NumIVMuls,
+                  C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
 }
 
 bool RISCVTTIImpl::isLegalMaskedCompressStore(Type *DataTy, Align Alignment) {

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https://github.com/llvm/llvm-project/pull/92296