[llvm] [SelectionDAG] Use ZERO_EXTEND_VECTOR_INREG for vectors (PR #92048)

[Simon Pilgrim via llvm-commits]

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@@ -1508,8 +1508,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) {
       !TLI.isOperationLegalOrCustom(Opcode, VT)) {
     SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
     Hi = DAG.getNode(ISD::VP_SHL, DL, VT, Hi, HiShift, Mask, EVL);
-    // FIXME: Replace it by vp operations.
-    Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
+    Lo = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, Lo);
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RKSimon wrote:

I don't think this can be correct - we've already extended Lo with GetPromotedInteger above, getZeroExtendInReg is just used to mask the lower bits.

https://github.com/llvm/llvm-project/pull/92048