[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[via llvm-commits]

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@@ -2784,6 +2784,25 @@ struct RegPairInfo {
 
 } // end anonymous namespace
 
+void verify(SmallVectorImpl<RegPairInfo> &RegPairs) {
+  auto IsPPR = [](const RegPairInfo &c) { return c.Reg1 == RegPairInfo::PPR; };
+  auto PPRBegin = std::find_if(RegPairs.begin(), RegPairs.end(), IsPPR);
+  auto IsZPR = [](const RegPairInfo &c) { return c.Type == RegPairInfo::ZPR; };
+  auto ZPRBegin = std::find_if(RegPairs.begin(), RegPairs.end(), IsZPR);
+  assert(!(PPRBegin < ZPRBegin) &&
+         "Expected callee save predicate to be handled first");
+}
+
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CarolineConcatto wrote:

> Does this work when there are no PPR registers to save (PPRBegin == RegPairs.end())?

If there is no PReg to save then it should be fine to clobber PReg.
AFAIU the check is  to avoid to spill/store the PRegs after ZRegs and fill/load PRegs before ZRegs. If there is not PReg to spill and fill then the compiler should be fine.

https://github.com/llvm/llvm-project/pull/77665