[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -2784,6 +2784,25 @@ struct RegPairInfo {
 
 } // end anonymous namespace
 
+void verify(SmallVectorImpl<RegPairInfo> &RegPairs) {
+  auto IsPPR = [](const RegPairInfo &c) { return c.Reg1 == RegPairInfo::PPR; };
+  auto PPRBegin = std::find_if(RegPairs.begin(), RegPairs.end(), IsPPR);
+  auto IsZPR = [](const RegPairInfo &c) { return c.Type == RegPairInfo::ZPR; };
+  auto ZPRBegin = std::find_if(RegPairs.begin(), RegPairs.end(), IsZPR);
+  assert(!(PPRBegin < ZPRBegin) &&
+         "Expected callee save predicate to be handled first");
+}
+
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sdesmalen-arm wrote:

Does this work when there are no PPR registers to save (PPRBegin == RegPairs.end())?

Additionally:
* You only need to check this when using a predicate reg to do the paired spill/fill instructions.
* nit: `verify` is quite a generic name, but the checks are rather specific. Maybe just inline this function where it is used?

https://github.com/llvm/llvm-project/pull/77665