[llvm] 0817754 - [RISCV] Improve testing of loads with offset in local-stack-slot-allocation.ll. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-05-13T11:02:13-07:00
New Revision: 08177541267fff84a96701fc5fc232eb4f12f9d9

URL: https://github.com/llvm/llvm-project/commit/08177541267fff84a96701fc5fc232eb4f12f9d9
DIFF: https://github.com/llvm/llvm-project/commit/08177541267fff84a96701fc5fc232eb4f12f9d9.diff

LOG: [RISCV] Improve testing of loads with offset in local-stack-slot-allocation.ll. NFC

The test we had didn't match it's description.

Now we have one test with a large offset that requires a virtual base register
and a test with a smaller offset that should not.

There is currently a bug that causes the offset to double counted
leading to the small case also using a virtual base register.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll b/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
index 40d08513e3cf3..c34e2bfdca08c 100644
--- a/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
+++ b/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
@@ -47,48 +47,69 @@ define void @use_frame_base_reg() {
 }
 
 ; Test containing a load with its own local offset. Make sure isFrameOffsetLegal
-; considers it and does not create a virtual base register.
+; considers it and creates a virtual base register.
 define void @load_with_offset() {
 ; RV32I-LABEL: load_with_offset:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 25
-; RV32I-NEXT:    addi a0, a0, -1792
-; RV32I-NEXT:    sub sp, sp, a0
-; RV32I-NEXT:    .cfi_def_cfa_offset 100608
-; RV32I-NEXT:    lui a0, 25
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lbu zero, -292(a0)
-; RV32I-NEXT:    lui a0, 24
-; RV32I-NEXT:    add a0, sp, a0
-; RV32I-NEXT:    lbu zero, 1704(a0)
-; RV32I-NEXT:    lui a0, 25
-; RV32I-NEXT:    addi a0, a0, -1792
-; RV32I-NEXT:    add sp, sp, a0
+; RV32I-NEXT:    addi sp, sp, -2048
+; RV32I-NEXT:    addi sp, sp, -464
+; RV32I-NEXT:    .cfi_def_cfa_offset 2512
+; RV32I-NEXT:    addi a0, sp, 2012
+; RV32I-NEXT:    lbu a1, 0(a0)
+; RV32I-NEXT:    sb a1, 0(a0)
+; RV32I-NEXT:    addi sp, sp, 2032
+; RV32I-NEXT:    addi sp, sp, 480
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_with_offset:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 25
-; RV64I-NEXT:    addiw a0, a0, -1792
-; RV64I-NEXT:    sub sp, sp, a0
-; RV64I-NEXT:    .cfi_def_cfa_offset 100608
-; RV64I-NEXT:    lui a0, 25
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    lbu zero, -292(a0)
-; RV64I-NEXT:    lui a0, 24
-; RV64I-NEXT:    add a0, sp, a0
-; RV64I-NEXT:    lbu zero, 1704(a0)
-; RV64I-NEXT:    lui a0, 25
-; RV64I-NEXT:    addiw a0, a0, -1792
-; RV64I-NEXT:    add sp, sp, a0
+; RV64I-NEXT:    addi sp, sp, -2048
+; RV64I-NEXT:    addi sp, sp, -464
+; RV64I-NEXT:    .cfi_def_cfa_offset 2512
+; RV64I-NEXT:    addi a0, sp, 2012
+; RV64I-NEXT:    lbu a1, 0(a0)
+; RV64I-NEXT:    sb a1, 0(a0)
+; RV64I-NEXT:    addi sp, sp, 2032
+; RV64I-NEXT:    addi sp, sp, 480
+; RV64I-NEXT:    ret
+
+  %va = alloca [2500 x i8], align 4
+  %va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 2000
+  %load = load volatile i8, ptr %va_gep, align 4
+  store volatile i8 %load, ptr %va_gep, align 4
+  ret void
+}
+
+; Test containing a load with its own local offset that is smaller than the
+; previous test case. Make sure we don't create a virtual base register.
+define void @load_with_offset2() {
+; RV32I-LABEL: load_with_offset2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -2048
+; RV32I-NEXT:    addi sp, sp, -464
+; RV32I-NEXT:    .cfi_def_cfa_offset 2512
+; RV32I-NEXT:    addi a0, sp, 1412
+; RV32I-NEXT:    lbu a1, 0(a0)
+; RV32I-NEXT:    sb a1, 0(a0)
+; RV32I-NEXT:    addi sp, sp, 2032
+; RV32I-NEXT:    addi sp, sp, 480
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: load_with_offset2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -2048
+; RV64I-NEXT:    addi sp, sp, -464
+; RV64I-NEXT:    .cfi_def_cfa_offset 2512
+; RV64I-NEXT:    addi a0, sp, 1412
+; RV64I-NEXT:    lbu a1, 0(a0)
+; RV64I-NEXT:    sb a1, 0(a0)
+; RV64I-NEXT:    addi sp, sp, 2032
+; RV64I-NEXT:    addi sp, sp, 480
 ; RV64I-NEXT:    ret
 
-  %va = alloca [100 x i8], align 4
-  %va1 = alloca [500 x i8], align 4
-  %large = alloca [100000 x i8]
-  %va_gep = getelementptr [100 x i8], ptr %va, i64 16
-  %va1_gep = getelementptr [100 x i8], ptr %va1, i64 0
+  %va = alloca [2500 x i8], align 4
+  %va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 1400
   %load = load volatile i8, ptr %va_gep, align 4
-  %load1 = load volatile i8, ptr %va1_gep, align 4
+  store volatile i8 %load, ptr %va_gep, align 4
   ret void
 }