[llvm] [X86][MC] Support Intel FRED and LKGS instructions. (PR #91909)

[Shengchen Kan via llvm-commits]

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@@ -212,6 +218,12 @@ def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
 
 let SchedRW = [WriteSystem] in {
 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
+// LKGS instructions
+let mayLoad = 1 in
+def LKGS16m : I<0x00, MRM6m, (outs), (ins i16mem:$src), "lkgs{w}\t$src",
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KanRobert wrote:

You need the side effect b/c

> loads the base address into the IA32_KERNEL_GS_BASE MSR
> instead of the GS segment’s descriptor cache


https://github.com/llvm/llvm-project/pull/91909