[llvm] [RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (PR #91860)
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llvm-commits at lists.llvm.org
Sat May 11 08:43:15 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Yeting Kuo (yetingk)
<details>
<summary>Changes</summary>
This patch is based on https://github.com/llvm/llvm-project/pull/91855. This patch inserts simple landing pad
([pr])before indirct jumps. And this also make option riscv-landing-pad-label influence this feature.
[pr]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
---
Full diff: https://github.com/llvm/llvm-project/pull/91860.diff
8 Files Affected:
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+2)
- (modified) llvm/lib/Target/RISCV/RISCV.h (+6)
- (added) llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp (+102)
- (added) llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp (+84)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
- (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+2)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+2)
- (added) llvm/test/CodeGen/RISCV/lpad.ll (+156)
``````````diff
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index 8715403f3839a..d876a1646d6d2 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -37,12 +37,14 @@ add_llvm_target(RISCVCodeGen
RISCVFoldMasks.cpp
RISCVFrameLowering.cpp
RISCVGatherScatterLowering.cpp
+ RISCVIndirectBranchTracking.cpp
RISCVInsertVSETVLI.cpp
RISCVInsertReadWriteCSR.cpp
RISCVInsertWriteVXRM.cpp
RISCVInstrInfo.cpp
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
+ RISCVLandingPadSetup.cpp
RISCVMachineFunctionInfo.cpp
RISCVMergeBaseOffset.cpp
RISCVOptWInstrs.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index d405395dcf9ec..5d50eb58deeed 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -31,9 +31,15 @@ void initializeRISCVCodeGenPreparePass(PassRegistry &);
FunctionPass *createRISCVDeadRegisterDefinitionsPass();
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &);
+FunctionPass *createRISCVIndirectBranchTrackingPass();
+void initializeRISCVIndirectBranchTrackingPass(PassRegistry &);
+
FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
CodeGenOptLevel OptLevel);
+FunctionPass *createRISCVLandingPadSetupPass();
+void initializeRISCVLandingPadSetupPass(PassRegistry &);
+
FunctionPass *createRISCVMakeCompressibleOptPass();
void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
new file mode 100644
index 0000000000000..ed854b6235fe1
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
@@ -0,0 +1,102 @@
+//===------ RISCVIndirectBranchTracking.cpp - Enables lpad mechanism ------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// The pass adds LPAD (AUIPC with rs1 = X0) machine instructions at the
+// beginning of each basic block or function that is referenced by an indrect
+// jump/call instruction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+
+using namespace llvm;
+
+cl::opt<uint32_t> PreferredLandingPadLabel(
+ "riscv-landing-pad-label", cl::ReallyHidden,
+ cl::desc("Use preferred fixed label for all labels"));
+
+namespace {
+class RISCVIndirectBranchTrackingPass : public MachineFunctionPass {
+public:
+ RISCVIndirectBranchTrackingPass() : MachineFunctionPass(ID) {}
+
+ StringRef getPassName() const override {
+ return "RISC-V Indirect Branch Tracking";
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+private:
+ static char ID;
+ const Align LpadAlign = Align(4);
+};
+
+} // end anonymous namespace
+
+char RISCVIndirectBranchTrackingPass::ID = 0;
+
+FunctionPass *llvm::createRISCVIndirectBranchTrackingPass() {
+ return new RISCVIndirectBranchTrackingPass();
+}
+
+static void emitLpad(MachineBasicBlock &MBB, const RISCVInstrInfo *TII,
+ uint32_t Label) {
+ auto I = MBB.begin();
+ BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(RISCV::AUIPC), RISCV::X0)
+ .addImm(Label);
+}
+
+bool RISCVIndirectBranchTrackingPass::runOnMachineFunction(
+ MachineFunction &MF) {
+ const auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
+ if (!Subtarget.hasStdExtZicfilp())
+ return false;
+
+ uint32_t Label = 0;
+ if (PreferredLandingPadLabel.getNumOccurrences() > 0) {
+ if (!isUInt<20>(PreferredLandingPadLabel))
+ report_fatal_error("riscv-landing-pad-label=<val>, <val> needs to fit in "
+ "unsigned 20-bits");
+ Label = PreferredLandingPadLabel;
+ }
+
+ // When trap is taken, landing pad is not needed.
+ if (MF.getFunction().hasFnAttribute("interrupt"))
+ return false;
+
+ bool Changed = false;
+ for (MachineBasicBlock &MBB : MF) {
+ if (&MBB == &MF.front()) {
+ Function &F = MF.getFunction();
+ if (F.hasAddressTaken() || !F.hasLocalLinkage()) {
+ emitLpad(MBB, TII, Label);
+ if (MF.getAlignment() < LpadAlign)
+ MF.setAlignment(LpadAlign);
+ Changed = true;
+ }
+ continue;
+ }
+
+ if (MBB.hasAddressTaken()) {
+ emitLpad(MBB, TII, Label);
+ if (MBB.getAlignment() < LpadAlign)
+ MBB.setAlignment(LpadAlign);
+ Changed = true;
+ }
+ }
+
+ return Changed;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
new file mode 100644
index 0000000000000..b577a1d70a3c2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
@@ -0,0 +1,84 @@
+//===------------ RISCVLandingPadSetup.cpp ---------------------------------==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This is a RISC-V pass to setup landing pad labels for indirect jumps.
+// Currently it is only supported fixed labels.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/InitializePasses.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-lpad-setup"
+#define PASS_NAME "RISC-V Landing Pad Setup"
+
+extern cl::opt<uint32_t> PreferredLandingPadLabel;
+
+namespace {
+
+class RISCVLandingPadSetup : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVLandingPadSetup() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &F) override;
+
+ StringRef getPassName() const override { return PASS_NAME; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
+} // end anonymous namespace
+
+bool RISCVLandingPadSetup::runOnMachineFunction(MachineFunction &MF) {
+ const auto &STI = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVInstrInfo &TII = *STI.getInstrInfo();
+
+ if (!STI.hasStdExtZicfilp())
+ return false;
+
+ bool Changed = false;
+ for (MachineBasicBlock &MBB : MF)
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
+ if (!MI.isIndirectBranch() &&
+ MI.getOpcode() != RISCV::PseudoCALLIndirectNonX7 &&
+ MI.getOpcode() != RISCV::PseudoTAILIndirectNonX7)
+ continue;
+ uint32_t Label = 0;
+ if (PreferredLandingPadLabel.getNumOccurrences() > 0) {
+ if (!isUInt<20>(PreferredLandingPadLabel))
+ report_fatal_error("riscv-landing-pad-label=<val>, <val> needs to fit in "
+ "unsigned 20-bits");
+ Label = PreferredLandingPadLabel;
+ }
+ BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::LUI), RISCV::X7)
+ .addImm(Label);
+ MachineInstrBuilder(MF, &MI).addUse(RISCV::X7, RegState::ImplicitKill);
+ Changed = true;
+ }
+
+ return Changed;
+}
+
+INITIALIZE_PASS(RISCVLandingPadSetup, DEBUG_TYPE, PASS_NAME, false, false)
+
+char RISCVLandingPadSetup::ID = 0;
+
+FunctionPass *llvm::createRISCVLandingPadSetupPass() {
+ return new RISCVLandingPadSetup();
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 7b2dcadc41917..d818c47bbf69a 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -511,6 +511,7 @@ void RISCVPassConfig::addPreEmitPass2() {
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
}
+ addPass(createRISCVIndirectBranchTrackingPass());
addPass(createRISCVExpandPseudoPass());
// Schedule the expansion of AMOs at the last possible moment, avoiding the
@@ -544,6 +545,7 @@ void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVInsertReadWriteCSRPass());
addPass(createRISCVInsertWriteVXRMPass());
addPass(createRISCVInsertVSETVLIPass());
+ addPass(createRISCVLandingPadSetupPass());
}
void RISCVPassConfig::addFastRegAlloc() {
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index c4a7f9562534c..7d5653718e5eb 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -43,6 +43,7 @@
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
; CHECK-NEXT: RISC-V Insert VSETVLI pass
+; CHECK-NEXT: RISC-V Landing Pad Setup
; CHECK-NEXT: Init Undef Pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
@@ -73,6 +74,7 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
+; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 4a71d3276d263..d046ebfa2dc0b 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -118,6 +118,7 @@
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
; CHECK-NEXT: RISC-V Insert VSETVLI pass
+; CHECK-NEXT: RISC-V Landing Pad Setup
; CHECK-NEXT: Detect Dead Lanes
; CHECK-NEXT: Init Undef Pass
; CHECK-NEXT: Process Implicit Definitions
@@ -196,6 +197,7 @@
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISC-V Zcmp move merging pass
; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
+; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
diff --git a/llvm/test/CodeGen/RISCV/lpad.ll b/llvm/test/CodeGen/RISCV/lpad.ll
new file mode 100644
index 0000000000000..263363173ece4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/lpad.ll
@@ -0,0 +1,156 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
+; Check indirectbr.
+ at __const.indirctbr.addr = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@indirctbr, %labelA), ptr blockaddress(@indirctbr, %labelB)], align 8
+define void @indirctbr(i32 %i, ptr %p) {
+; RV32-LABEL: indirctbr:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: lpad 0
+; RV32-NEXT: slli a0, a0, 2
+; RV32-NEXT: lui a2, %hi(.L__const.indirctbr.addr)
+; RV32-NEXT: addi a2, a2, %lo(.L__const.indirctbr.addr)
+; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: lw a0, 0(a0)
+; RV32-NEXT: lui t2, 0
+; RV32-NEXT: jr a0
+; RV32-NEXT: .p2align 2
+; RV32-NEXT: .Ltmp3: # Block address taken
+; RV32-NEXT: .LBB0_1: # %labelA
+; RV32-NEXT: lpad 0
+; RV32-NEXT: li a0, 1
+; RV32-NEXT: sw a0, 0(a1)
+; RV32-NEXT: .p2align 2
+; RV32-NEXT: .Ltmp4: # Block address taken
+; RV32-NEXT: .LBB0_2: # %labelB
+; RV32-NEXT: lpad 0
+; RV32-NEXT: li a0, 2
+; RV32-NEXT: sw a0, 0(a1)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: indirctbr:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: lpad 0
+; RV64-NEXT: lui a2, %hi(.L__const.indirctbr.addr)
+; RV64-NEXT: addi a2, a2, %lo(.L__const.indirctbr.addr)
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: ld a0, 0(a0)
+; RV64-NEXT: lui t2, 0
+; RV64-NEXT: jr a0
+; RV64-NEXT: .p2align 2
+; RV64-NEXT: .Ltmp3: # Block address taken
+; RV64-NEXT: .LBB0_1: # %labelA
+; RV64-NEXT: lpad 0
+; RV64-NEXT: li a0, 1
+; RV64-NEXT: sw a0, 0(a1)
+; RV64-NEXT: .p2align 2
+; RV64-NEXT: .Ltmp4: # Block address taken
+; RV64-NEXT: .LBB0_2: # %labelB
+; RV64-NEXT: lpad 0
+; RV64-NEXT: li a0, 2
+; RV64-NEXT: sw a0, 0(a1)
+; RV64-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds [2 x ptr], ptr @__const.indirctbr.addr, i64 0, i32 %i
+ %0 = load ptr, ptr %arrayidx
+ indirectbr ptr %0, [label %labelA, label %labelB]
+
+labelA: ; preds = %entry
+ store volatile i32 1, ptr %p
+ br label %labelB
+
+labelB: ; preds = %labelA, %entry
+ store volatile i32 2, ptr %p
+ ret void
+}
+
+; Check call.
+define void @call(ptr %0) {
+; CHECK-LABEL: call:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: lui t2, 0
+; CHECK-NEXT: jr a0
+ tail call void %0()
+ ret void
+}
+
+; Check invoke.
+declare dso_local i32 @__gxx_personality_v0(...)
+define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
+; RV32-LABEL: invoke:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: lpad 0
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: .Ltmp0:
+; RV32-NEXT: lui t2, 0
+; RV32-NEXT: jalr a0
+; RV32-NEXT: .Ltmp1:
+; RV32-NEXT: .LBB2_1: # %try.cont
+; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+; RV32-NEXT: .LBB2_2: # %lpad
+; RV32-NEXT: .Ltmp2:
+; RV32-NEXT: j .LBB2_1
+;
+; RV64-LABEL: invoke:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: lpad 0
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: .Ltmp0:
+; RV64-NEXT: lui t2, 0
+; RV64-NEXT: jalr a0
+; RV64-NEXT: .Ltmp1:
+; RV64-NEXT: .LBB2_1: # %try.cont
+; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: ret
+; RV64-NEXT: .LBB2_2: # %lpad
+; RV64-NEXT: .Ltmp2:
+; RV64-NEXT: j .LBB2_1
+entry:
+ invoke void %f() to label %try.cont unwind label %lpad
+
+lpad:
+ %0 = landingpad { ptr, i32 } cleanup
+ br label %try.cont
+
+try.cont:
+ ret void
+}
+
+; Check internal linkage function.
+define internal void @internal() {
+; CHECK-LABEL: internal:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ ret void
+}
+
+; Check internal linkage function with taken address.
+ at foo = constant ptr @internal2
+define internal void @internal2() {
+; CHECK-LABEL: internal2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lpad 0
+; CHECK-NEXT: ret
+ ret void
+}
+
+; Check interrupt function does not need landing pad.
+define void @interrupt() "interrupt"="user" {
+; CHECK-LABEL: interrupt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mret
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/91860
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