[llvm] [AMDGPU] Fix broken MIR generated by gfx11 simulated trap lowering (PR #91652)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat May 11 00:35:12 PDT 2024
================
@@ -2065,16 +2061,33 @@ MachineBasicBlock *SIInstrInfo::insertSimulatedTrap(MachineRegisterInfo &MRI,
.addImm(AMDGPU::SendMsg::ID_INTERRUPT);
BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0)
.addUse(AMDGPU::TTMP2);
- BuildMI(MBB, MI, DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoop);
+
+ MachineBasicBlock *HaltLoop = MF->CreateMachineBasicBlock();
+ MF->push_back(HaltLoop);
+ HaltLoop->addSuccessor(HaltLoop);
BuildMI(*HaltLoop, HaltLoop->end(), DL, get(AMDGPU::S_SETHALT)).addImm(5);
BuildMI(*HaltLoop, HaltLoop->end(), DL, get(AMDGPU::S_BRANCH))
.addMBB(HaltLoop);
- if (SplitBB != &MBB)
- MBB.removeSuccessor(SplitBB);
+ if (MBB.succ_empty() && std::next(MI.getIterator()) == MBB.end()) {
+ BuildMI(MBB, MI, DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoop);
+ MBB.addSuccessor(HaltLoop);
+ return &MBB;
+ }
+
+ // HACK: There are some instructions/successors following the trap. Since uses
+ // of virtual registers after the trap that were defined before the trap must
+ // be dominated by their definitions, we need the uses to be successors (even
+ // though they're unreachable in practice). This needs to be represented by a
+ // dummy cmp_eq and cbranch to convince analyzeBranch that SplitBB should
+ // indeed be considered a successor.
+ MachineBasicBlock *SplitBB = MBB.splitAt(MI, /*UpdateLiveIns=*/false);
+ BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_EQ_U32))
+ .addUse(SetWaveAbortBit)
+ .addUse(SetWaveAbortBit);
+ BuildMI(MBB, MI, DL, get(AMDGPU::S_CBRANCH_SCC1)).addMBB(HaltLoop);
----------------
arsenm wrote:
This is just an unconditional branch
https://github.com/llvm/llvm-project/pull/91652
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