[llvm] 7f3e378 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-05-10T22:40:23+01:00
New Revision: 7f3e3785d0be00c727e3d2938b6348748499de99

URL: https://github.com/llvm/llvm-project/commit/7f3e3785d0be00c727e3d2938b6348748499de99
DIFF: https://github.com/llvm/llvm-project/commit/7f3e3785d0be00c727e3d2938b6348748499de99.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9fbafba9fea7d..a044b6dc4838a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1095,12 +1095,12 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
         N1.getOperand(0).getOpcode() == ISD::VSCALE &&
         isa<ConstantSDNode>(N1.getOperand(1)))) &&
       N1.getValueType().getFixedSizeInBits() <= 64) {
-    int64_t ScalableOffset =
-        N1.getOpcode() == ISD::VSCALE
-            ? N1.getConstantOperandVal(0)
-            : (N1.getOperand(0).getConstantOperandVal(0) *
-               (N1.getOpcode() == ISD::SHL ? (1 << N1.getConstantOperandVal(1))
-                                           : N1.getConstantOperandVal(1)));
+    int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE
+                                 ? N1.getConstantOperandVal(0)
+                                 : (N1.getOperand(0).getConstantOperandVal(0) *
+                                    (N1.getOpcode() == ISD::SHL
+                                         ? (1LL << N1.getConstantOperandVal(1))
+                                         : N1.getConstantOperandVal(1)));
     if (Opc == ISD::SUB)
       ScalableOffset = -ScalableOffset;
     if (all_of(N->uses(), [&](SDNode *Node) {