[llvm] [LLVM][CodeGen][SVE] Improve custom lowering for EXTRACT_SUBVECTOR. (PR #90963)

[Paul Walker via llvm-commits]

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@@ -177,18 +177,19 @@ define void @ucvtf_v8i16_v8f64(ptr %a, ptr %b) {
 ; CHECK-NEXT:    uunpklo z1.s, z0.h
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    uunpklo z2.d, z1.s
-; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
-; CHECK-NEXT:    uunpklo z3.d, z0.s
+; CHECK-NEXT:    mov z3.d, z1.d
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paulwalker-arm wrote:

I've investigated this (via --debug=only=isel) and the only difference in the DAG prior to instruction selection is a few nodes having different numerical IDs.  The extra mov instruction disappears when using a Neoverse scheduling model so this looks like an existing issue with in-order scheduling.

Given these are streaming mode functions I believe  the current output is acceptable but please shout if you think otherwise.

https://github.com/llvm/llvm-project/pull/90963