[llvm] ISel/AArch64: custom lower vector ISD::[L]LRINT (PR #89035)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri May 10 00:43:00 PDT 2024
================
@@ -1,534 +1,894 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+sve \
+; RUN: -aarch64-sve-vector-bits-min=256 | FileCheck --check-prefixes=CHECK-i32 %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+sve \
+; RUN: -aarch64-sve-vector-bits-min=256 | FileCheck --check-prefixes=CHECK-i64 %s
-define <1 x i64> @lrint_v1f16(<1 x half> %x) {
-; CHECK-LABEL: lrint_v1f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: frintx h0, h0
-; CHECK-NEXT: fcvtzs x8, h0
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
- %a = call <1 x i64> @llvm.lrint.v1i64.v1f16(<1 x half> %x)
- ret <1 x i64> %a
+define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
+; CHECK-i32-LABEL: lrint_v1f16:
+; CHECK-i32: // %bb.0:
+; CHECK-i32-NEXT: frintx h0, h0
+; CHECK-i32-NEXT: fcvtzs w8, h0
+; CHECK-i32-NEXT: fmov s0, w8
+; CHECK-i32-NEXT: ret
+;
+; CHECK-i64-LABEL: lrint_v1f16:
+; CHECK-i64: // %bb.0:
+; CHECK-i64-NEXT: frintx h0, h0
+; CHECK-i64-NEXT: fcvtzs x8, h0
+; CHECK-i64-NEXT: fmov d0, x8
+; CHECK-i64-NEXT: ret
+ %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)
+ ret <1 x iXLen> %a
}
-declare <1 x i64> @llvm.lrint.v1i64.v1f16(<1 x half>)
+declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half>)
-define <2 x i64> @lrint_v2f16(<2 x half> %x) {
-; CHECK-LABEL: lrint_v2f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
-; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT: ret
- %a = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> %x)
- ret <2 x i64> %a
+define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
+; CHECK-i32-LABEL: lrint_v2f16:
+; CHECK-i32: // %bb.0:
+; CHECK-i32-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i32-NEXT: mov h1, v0.h[1]
+; CHECK-i32-NEXT: frintx h0, h0
+; CHECK-i32-NEXT: frintx h1, h1
+; CHECK-i32-NEXT: fcvtzs w8, h0
+; CHECK-i32-NEXT: fcvtzs w9, h1
+; CHECK-i32-NEXT: fmov s0, w8
+; CHECK-i32-NEXT: mov v0.s[1], w9
+; CHECK-i32-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-i32-NEXT: ret
+;
+; CHECK-i64-LABEL: lrint_v2f16:
+; CHECK-i64: // %bb.0:
+; CHECK-i64-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i64-NEXT: mov h1, v0.h[1]
+; CHECK-i64-NEXT: frintx h0, h0
+; CHECK-i64-NEXT: frintx h1, h1
+; CHECK-i64-NEXT: fcvtzs x8, h0
+; CHECK-i64-NEXT: fcvtzs x9, h1
+; CHECK-i64-NEXT: fmov d0, x8
+; CHECK-i64-NEXT: mov v0.d[1], x9
+; CHECK-i64-NEXT: ret
+ %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)
+ ret <2 x iXLen> %a
}
-declare <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half>)
+declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half>)
-define <4 x i64> @lrint_v4f16(<4 x half> %x) {
-; CHECK-LABEL: lrint_v4f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
-; CHECK-NEXT: mov z1.d, z0.d
-; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
-; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
-; CHECK-NEXT: ret
- %a = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> %x)
- ret <4 x i64> %a
+define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
+; CHECK-i32-LABEL: lrint_v4f16:
+; CHECK-i32: // %bb.0:
+; CHECK-i32-NEXT: frintx v0.4h, v0.4h
+; CHECK-i32-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i32-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-i32-NEXT: ret
+;
+; CHECK-i64-LABEL: lrint_v4f16:
+; CHECK-i64: // %bb.0:
+; CHECK-i64-NEXT: frintx v0.4h, v0.4h
+; CHECK-i64-NEXT: mov h1, v0.h[2]
+; CHECK-i64-NEXT: mov h2, v0.h[3]
+; CHECK-i64-NEXT: mov h3, v0.h[1]
+; CHECK-i64-NEXT: fcvtzs x9, h0
+; CHECK-i64-NEXT: fcvtzs x8, h1
+; CHECK-i64-NEXT: fcvtzs x10, h2
+; CHECK-i64-NEXT: fcvtzs x11, h3
+; CHECK-i64-NEXT: fmov d0, x9
+; CHECK-i64-NEXT: fmov d1, x8
+; CHECK-i64-NEXT: mov v0.d[1], x11
+; CHECK-i64-NEXT: mov v1.d[1], x10
+; CHECK-i64-NEXT: ret
+ %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
+ ret <4 x iXLen> %a
}
-declare <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half>)
+declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
-define <8 x i64> @lrint_v8f16(<8 x half> %x) {
-; CHECK-LABEL: lrint_v8f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.h
-; CHECK-NEXT: mov z1.d, z0.d
-; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
-; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT: mov z3.d, z2.d
-; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
-; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
-; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
-; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
-; CHECK-NEXT: ret
- %a = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> %x)
- ret <8 x i64> %a
+define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
+; CHECK-i32-LABEL: lrint_v8f16:
+; CHECK-i32: // %bb.0:
+; CHECK-i32-NEXT: frintx v2.8h, v0.8h
+; CHECK-i32-NEXT: mov h0, v2.h[4]
+; CHECK-i32-NEXT: mov h1, v2.h[5]
+; CHECK-i32-NEXT: mov h3, v2.h[1]
+; CHECK-i32-NEXT: fcvtzs w9, h2
+; CHECK-i32-NEXT: mov h4, v2.h[6]
+; CHECK-i32-NEXT: fcvtzs w8, h0
+; CHECK-i32-NEXT: mov h0, v2.h[2]
+; CHECK-i32-NEXT: fcvtzs w10, h1
+; CHECK-i32-NEXT: fcvtzs w11, h3
+; CHECK-i32-NEXT: mov h3, v2.h[7]
+; CHECK-i32-NEXT: fcvtzs w12, h4
+; CHECK-i32-NEXT: mov h2, v2.h[3]
+; CHECK-i32-NEXT: fcvtzs w13, h0
+; CHECK-i32-NEXT: fmov s0, w9
+; CHECK-i32-NEXT: fmov s1, w8
+; CHECK-i32-NEXT: fcvtzs w8, h3
+; CHECK-i32-NEXT: fcvtzs w9, h2
+; CHECK-i32-NEXT: mov v0.s[1], w11
+; CHECK-i32-NEXT: mov v1.s[1], w10
+; CHECK-i32-NEXT: mov v0.s[2], w13
+; CHECK-i32-NEXT: mov v1.s[2], w12
+; CHECK-i32-NEXT: mov v0.s[3], w9
+; CHECK-i32-NEXT: mov v1.s[3], w8
+; CHECK-i32-NEXT: ret
+;
+; CHECK-i64-LABEL: lrint_v8f16:
+; CHECK-i64: // %bb.0:
+; CHECK-i64-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-NEXT: frintx v0.4h, v0.4h
+; CHECK-i64-NEXT: frintx v1.4h, v1.4h
+; CHECK-i64-NEXT: mov h4, v0.h[2]
+; CHECK-i64-NEXT: mov h2, v0.h[1]
+; CHECK-i64-NEXT: mov h7, v0.h[3]
+; CHECK-i64-NEXT: fcvtzs x8, h0
+; CHECK-i64-NEXT: mov h3, v1.h[2]
+; CHECK-i64-NEXT: mov h5, v1.h[3]
+; CHECK-i64-NEXT: mov h6, v1.h[1]
+; CHECK-i64-NEXT: fcvtzs x11, h1
+; CHECK-i64-NEXT: fcvtzs x12, h4
+; CHECK-i64-NEXT: fcvtzs x9, h2
+; CHECK-i64-NEXT: fcvtzs x15, h7
+; CHECK-i64-NEXT: fmov d0, x8
+; CHECK-i64-NEXT: fcvtzs x10, h3
+; CHECK-i64-NEXT: fcvtzs x13, h5
+; CHECK-i64-NEXT: fcvtzs x14, h6
+; CHECK-i64-NEXT: fmov d1, x12
+; CHECK-i64-NEXT: fmov d2, x11
+; CHECK-i64-NEXT: mov v0.d[1], x9
+; CHECK-i64-NEXT: fmov d3, x10
+; CHECK-i64-NEXT: mov v1.d[1], x15
+; CHECK-i64-NEXT: mov v2.d[1], x14
+; CHECK-i64-NEXT: mov v3.d[1], x13
+; CHECK-i64-NEXT: ret
+ %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
+ ret <8 x iXLen> %a
}
-declare <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half>)
+declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half>)
-define <16 x i64> @lrint_v16i64_v16f16(<16 x half> %x) {
-; CHECK-LABEL: lrint_v16i64_v16f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: frintx v2.4h, v2.4h
-; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: uunpklo z2.s, z2.h
-; CHECK-NEXT: uunpklo z3.s, z3.h
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: uunpklo z2.d, z2.s
-; CHECK-NEXT: uunpklo z3.d, z3.s
-; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
-; CHECK-NEXT: movprfx z4, z1
-; CHECK-NEXT: fcvtzs z4.d, p0/m, z1.h
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
-; CHECK-NEXT: movprfx z6, z3
-; CHECK-NEXT: fcvtzs z6.d, p0/m, z3.h
-; CHECK-NEXT: mov z1.d, z0.d
-; CHECK-NEXT: mov z5.d, z4.d
-; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
-; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT: mov z3.d, z2.d
-; CHECK-NEXT: mov z7.d, z6.d
-; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
-; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
-; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
-; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
-; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
-; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
-; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
-; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
-; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
-; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
-; CHECK-NEXT: ret
- %a = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> %x)
- ret <16 x i64> %a
+define <16 x iXLen> @lrint_v16iXLen_v16f16(<16 x half> %x) {
----------------
davemgreen wrote:
This isn't getting CHECK lines? Were they all conflicting?
https://github.com/llvm/llvm-project/pull/89035
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