[llvm] [RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (PR #91701)

[Luke Lau via llvm-commits]

================
@@ -937,15 +937,15 @@ declare <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32>, i1 immar
 define <vscale x 16 x i32> @vp_ctlz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vp_ctlz_nxv16i32:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsrmi a1, 1
----------------
lukel97 wrote:

To repeat the comment on this diff from the previous PR: https://github.com/llvm/llvm-project/pull/91440#discussion_r1595829693

We have ever so slightly higher register pressure here in the range between the fsrmi and the vsetvli.

But if register pressure was actually a problem here, then I think the onus should fall on MachineScheduler to reorder these. So I'm not concerned about this

https://github.com/llvm/llvm-project/pull/91701