[llvm] [AArch64][GlobalISel] Select G_ICMP instruction through TableGen (PR #89932)

[Amara Emerson via llvm-commits]

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@@ -128,40 +959,6 @@ entry:
   ret <3 x i64> %s
 }
 
-define <4 x i64> @v4i64_i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %d, <4 x i64> %e) {
-; CHECK-SD-LABEL: v4i64_i64:
-; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    cmgt v1.2d, v3.2d, v1.2d
-; CHECK-SD-NEXT:    cmgt v0.2d, v2.2d, v0.2d
-; CHECK-SD-NEXT:    bsl v1.16b, v5.16b, v7.16b
-; CHECK-SD-NEXT:    bsl v0.16b, v4.16b, v6.16b
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: v4i64_i64:
-; CHECK-GI:       // %bb.0: // %entry
-; CHECK-GI-NEXT:    cmgt v0.2d, v2.2d, v0.2d
-; CHECK-GI-NEXT:    cmgt v1.2d, v3.2d, v1.2d
-; CHECK-GI-NEXT:    bsl v0.16b, v4.16b, v6.16b
-; CHECK-GI-NEXT:    bsl v1.16b, v5.16b, v7.16b
-; CHECK-GI-NEXT:    ret
-entry:
-  %c = icmp slt <4 x i64> %a, %b
-  %s = select <4 x i1> %c, <4 x i64> %d, <4 x i64> %e
-  ret <4 x i64> %s
-}
-
-define <2 x i32> @v2i32_i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %d, <2 x i32> %e) {
-; CHECK-LABEL: v2i32_i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    cmgt v0.2s, v1.2s, v0.2s
-; CHECK-NEXT:    bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT:    ret
-entry:
-  %c = icmp slt <2 x i32> %a, %b
-  %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e
-  ret <2 x i32> %s
-}
-
 define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32> %e) {
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aemerson wrote:

Ah makes sense, feel free to delete them if you like then.

https://github.com/llvm/llvm-project/pull/89932