[llvm] [BOLT][NFC] Rename DispExpr to JTBaseDispExpr in analyzeIndirectBranch (PR #91659)
Amir Ayupov via llvm-commits
llvm-commits at lists.llvm.org
Thu May 9 14:31:16 PDT 2024
https://github.com/aaupov created https://github.com/llvm/llvm-project/pull/91659
Test Plan: NFC
>From d280d8b9ee1aa769124e6440c801434054aff80c Mon Sep 17 00:00:00 2001
From: Amir Ayupov <aaupov at fb.com>
Date: Thu, 9 May 2024 14:31:04 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
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Created using spr 1.3.4
---
bolt/include/bolt/Core/MCPlusBuilder.h | 2 +-
bolt/lib/Core/BinaryFunction.cpp | 12 ++++++------
bolt/lib/Passes/IndirectCallPromotion.cpp | 10 +++++-----
bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp | 15 ++++++++-------
bolt/lib/Target/X86/X86MCPlusBuilder.cpp | 15 ++++++++-------
5 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h
index f7614cf9ac977..f1318d2f9be13 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -1472,7 +1472,7 @@ class MCPlusBuilder {
InstructionIterator End, const unsigned PtrSize,
MCInst *&MemLocInstr, unsigned &BaseRegNum,
unsigned &IndexRegNum, int64_t &DispValue,
- const MCExpr *&DispExpr, MCInst *&PCRelBaseOut) const {
+ const MCExpr *&JTBaseDispExpr, MCInst *&PCRelBaseOut) const {
llvm_unreachable("not implemented");
return IndirectBranchType::UNKNOWN;
}
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index de34421ebeb08..c34b98484b888 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -785,7 +785,7 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction, unsigned Size,
unsigned BaseRegNum, IndexRegNum;
int64_t DispValue;
- const MCExpr *DispExpr;
+ const MCExpr *JTBaseDispExpr;
// In AArch, identify the instruction adding the PC-relative offset to
// jump table entries to correctly decode it.
@@ -810,7 +810,7 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction, unsigned Size,
IndirectBranchType BranchType = BC.MIB->analyzeIndirectBranch(
Instruction, Begin, Instructions.end(), PtrSize, MemLocInstr, BaseRegNum,
- IndexRegNum, DispValue, DispExpr, PCRelBaseInstr);
+ IndexRegNum, DispValue, JTBaseDispExpr, PCRelBaseInstr);
if (BranchType == IndirectBranchType::UNKNOWN && !MemLocInstr)
return BranchType;
@@ -853,10 +853,10 @@ BinaryFunction::processIndirectBranch(MCInst &Instruction, unsigned Size,
// RIP-relative addressing should be converted to symbol form by now
// in processed instructions (but not in jump).
- if (DispExpr) {
+ if (JTBaseDispExpr) {
const MCSymbol *TargetSym;
uint64_t TargetOffset;
- std::tie(TargetSym, TargetOffset) = BC.MIB->getTargetSymbolInfo(DispExpr);
+ std::tie(TargetSym, TargetOffset) = BC.MIB->getTargetSymbolInfo(JTBaseDispExpr);
ErrorOr<uint64_t> SymValueOrError = BC.getSymbolValue(*TargetSym);
assert(SymValueOrError && "global symbol needs a value");
ArrayStart = *SymValueOrError + TargetOffset;
@@ -1868,11 +1868,11 @@ bool BinaryFunction::postProcessIndirectBranches(
MCInst *MemLocInstr;
unsigned BaseRegNum, IndexRegNum;
int64_t DispValue;
- const MCExpr *DispExpr;
+ const MCExpr *JTBaseDispExpr;
MCInst *PCRelBaseInstr;
IndirectBranchType Type = BC.MIB->analyzeIndirectBranch(
Instr, BB.begin(), II, PtrSize, MemLocInstr, BaseRegNum,
- IndexRegNum, DispValue, DispExpr, PCRelBaseInstr);
+ IndexRegNum, DispValue, JTBaseDispExpr, PCRelBaseInstr);
if (Type != IndirectBranchType::UNKNOWN || MemLocInstr != nullptr)
continue;
diff --git a/bolt/lib/Passes/IndirectCallPromotion.cpp b/bolt/lib/Passes/IndirectCallPromotion.cpp
index 55eede641fd2f..72a4cb30c2a79 100644
--- a/bolt/lib/Passes/IndirectCallPromotion.cpp
+++ b/bolt/lib/Passes/IndirectCallPromotion.cpp
@@ -388,11 +388,11 @@ IndirectCallPromotion::maybeGetHotJumpTableTargets(BinaryBasicBlock &BB,
MCInst *PCRelBaseOut;
unsigned BaseReg, IndexReg;
int64_t DispValue;
- const MCExpr *DispExpr;
+ const MCExpr *JTBaseDispExpr;
MutableArrayRef<MCInst> Insts(&BB.front(), &CallInst);
const IndirectBranchType Type = BC.MIB->analyzeIndirectBranch(
CallInst, Insts.begin(), Insts.end(), BC.AsmInfo->getCodePointerSize(),
- MemLocInstr, BaseReg, IndexReg, DispValue, DispExpr, PCRelBaseOut);
+ MemLocInstr, BaseReg, IndexReg, DispValue, JTBaseDispExpr, PCRelBaseOut);
assert(MemLocInstr && "There should always be a load for jump tables");
if (!MemLocInstr)
@@ -413,7 +413,7 @@ IndirectCallPromotion::maybeGetHotJumpTableTargets(BinaryBasicBlock &BB,
<< "BaseReg = " << BC.MRI->getName(BaseReg) << ", "
<< "IndexReg = " << BC.MRI->getName(IndexReg) << ", "
<< "DispValue = " << Twine::utohexstr(DispValue) << ", "
- << "DispExpr = " << DispExpr << ", "
+ << "DispExpr = " << JTBaseDispExpr << ", "
<< "MemLocInstr = ";
BC.printInstruction(dbgs(), *MemLocInstr, 0, &Function);
dbgs() << "\n";
@@ -432,9 +432,9 @@ IndirectCallPromotion::maybeGetHotJumpTableTargets(BinaryBasicBlock &BB,
MemoryAccessProfile &MemAccessProfile = ErrorOrMemAccessProfile.get();
uint64_t ArrayStart;
- if (DispExpr) {
+ if (JTBaseDispExpr) {
ErrorOr<uint64_t> DispValueOrError =
- BC.getSymbolValue(*BC.MIB->getTargetSymbol(DispExpr));
+ BC.getSymbolValue(*BC.MIB->getTargetSymbol(JTBaseDispExpr));
assert(DispValueOrError && "global symbol needs a value");
ArrayStart = *DispValueOrError;
} else {
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 0ae9d3668b93b..97c4510f77f1e 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -832,16 +832,17 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return Uses;
}
- IndirectBranchType analyzeIndirectBranch(
- MCInst &Instruction, InstructionIterator Begin, InstructionIterator End,
- const unsigned PtrSize, MCInst *&MemLocInstrOut, unsigned &BaseRegNumOut,
- unsigned &IndexRegNumOut, int64_t &DispValueOut,
- const MCExpr *&DispExprOut, MCInst *&PCRelBaseOut) const override {
+ IndirectBranchType
+ analyzeIndirectBranch(MCInst &Instruction, InstructionIterator Begin,
+ InstructionIterator End, const unsigned PtrSize,
+ MCInst *&MemLocInstrOut, unsigned &BaseRegNumOut,
+ unsigned &IndexRegNumOut, int64_t &DispValueOut,
+ const MCExpr *&JTBaseDispExprOut, MCInst *&PCRelBaseOut) const override {
MemLocInstrOut = nullptr;
BaseRegNumOut = AArch64::NoRegister;
IndexRegNumOut = AArch64::NoRegister;
DispValueOut = 0;
- DispExprOut = nullptr;
+ JTBaseDispExprOut = nullptr;
// An instruction referencing memory used by jump instruction (directly or
// via register). This location could be an array of function pointers
@@ -861,7 +862,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
MemLocInstrOut = MemLocInstr;
DispValueOut = DispValue;
- DispExprOut = DispExpr;
+ JTBaseDispExprOut = DispExpr;
PCRelBaseOut = PCRelBase;
return IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE;
}
diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
index 8b1894953f375..e64ed809810e8 100644
--- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -2003,11 +2003,12 @@ class X86MCPlusBuilder : public MCPlusBuilder {
MemLocInstr);
}
- IndirectBranchType analyzeIndirectBranch(
- MCInst &Instruction, InstructionIterator Begin, InstructionIterator End,
- const unsigned PtrSize, MCInst *&MemLocInstrOut, unsigned &BaseRegNumOut,
- unsigned &IndexRegNumOut, int64_t &DispValueOut,
- const MCExpr *&DispExprOut, MCInst *&PCRelBaseOut) const override {
+ IndirectBranchType
+ analyzeIndirectBranch(MCInst &Instruction, InstructionIterator Begin,
+ InstructionIterator End, const unsigned PtrSize,
+ MCInst *&MemLocInstrOut, unsigned &BaseRegNumOut,
+ unsigned &IndexRegNumOut, int64_t &DispValueOut,
+ const MCExpr *&JTBaseDispExpr, MCInst *&PCRelBaseOut) const override {
// Try to find a (base) memory location from where the address for
// the indirect branch is loaded. For X86-64 the memory will be specified
// in the following format:
@@ -2033,7 +2034,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
BaseRegNumOut = X86::NoRegister;
IndexRegNumOut = X86::NoRegister;
DispValueOut = 0;
- DispExprOut = nullptr;
+ JTBaseDispExpr = nullptr;
std::reverse_iterator<InstructionIterator> II(End);
std::reverse_iterator<InstructionIterator> IE(Begin);
@@ -2093,7 +2094,7 @@ class X86MCPlusBuilder : public MCPlusBuilder {
BaseRegNumOut = MO->BaseRegNum;
IndexRegNumOut = MO->IndexRegNum;
DispValueOut = MO->DispImm;
- DispExprOut = MO->DispExpr;
+ JTBaseDispExpr = MO->DispExpr;
if ((MO->BaseRegNum != X86::NoRegister && MO->BaseRegNum != RIPRegister) ||
MO->SegRegNum != X86::NoRegister)
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