[llvm] [RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c4-c2), c4). (PR #91638)

[Philip Reames via llvm-commits]

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@@ -1350,6 +1350,21 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
             return;
           }
         }
+
+        // Turn (and (shl x, c2), c1) -> (slli_uw (srli x, c4-c2), c4) where c1
+        // is shifted mask with 32 set bits and c4 trailing zeros.
+        unsigned Trailing = llvm::countr_zero(C1);
+        if (Leading + Trailing == 32 && C2 < Trailing &&
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preames wrote:

Do we need a !IsCANDI check here?

https://github.com/llvm/llvm-project/pull/91638