[llvm] [RISCV] Inhibit DAG folding shl through zext.w pattern with zba (PR #91626)

[Philip Reames via llvm-commits]

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@@ -2891,8 +2890,7 @@ define i64 @srli_slliw(i64 %1) {
 ;
 ; RV64ZBA-LABEL: srli_slliw:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    slli a0, a0, 2
-; RV64ZBA-NEXT:    srli a0, a0, 4
+; RV64ZBA-NEXT:    srli a0, a0, 2
 ; RV64ZBA-NEXT:    slli.uw a0, a0, 4
 ; RV64ZBA-NEXT:    ret
 entry:
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preames wrote:

Yeah, this was excessive reduction apparently.  

The fact instcombine prefers the opposite form does hint that we should maybe (also?) do the late match.  I was really hoping not to have to write that code...

https://github.com/llvm/llvm-project/pull/91626