[llvm] [RISCV] Inhibit DAG folding shl through zext.w pattern with zba (PR #91626)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff d0bafb5435d5ebd90cdf965a9b35bdfa05dde23b 2221121e138ef693fea3e8c4594fe2fc559820e1 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 60b21fb508..cf682d9129 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17143,8 +17143,9 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
   }
 
   // Don't break slli.uw patterns.
-  if (Subtarget.hasStdExtZba() && Ty.isScalarInteger() && N->getOpcode() == ISD::SHL &&
-      N0.getOpcode() == ISD::AND && isa<ConstantSDNode>(N0.getOperand(1)) &&
+  if (Subtarget.hasStdExtZba() && Ty.isScalarInteger() &&
+      N->getOpcode() == ISD::SHL && N0.getOpcode() == ISD::AND &&
+      isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.getConstantOperandVal(1) == UINT64_C(0xffffffff))
     return false;
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/91626