[llvm] [RISC-V] Limit vscale interleaving to addrspace 0. (PR #91573)

[Luke Lau via llvm-commits]

lukel97 wrote:

We have separate segmented load/store intrinsics for fixed length vectors, which have `llvm_anyptr_ty` in their signature whereas the regular scalar ones just have `llvm_ptr_ty`: https://reviews.llvm.org/D119834. Given that no other intrinsics support other address spaces should we just update the fixed length ones to use `llvm_ptr_ty` too?

(As an aside I got very confused when I saw I had added those intrinsics, but turns out that's not me: their username is luke957 not lukel97!)

https://github.com/llvm/llvm-project/pull/91573