[llvm] ISel/AArch64/SVE: custom lower vector ISD::[L]LRINT (PR #89035)

[Paul Walker via llvm-commits]

================
@@ -4362,6 +4366,40 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
   return DAG.getNode(ISD::TRUNCATE, DL, DstVT, Sat);
 }
 
+SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+  SDValue Src = Op.getOperand(0);
+  SDLoc DL(Op);
+
+  assert(VT.isVector() && "Expected vector type");
+
+  EVT ContainerVT = VT;
+  EVT SrcVT = Src.getValueType();
+  EVT CastVT =
+      ContainerVT.changeVectorElementType(SrcVT.getVectorElementType());
+
+  if (VT.isFixedLengthVector()) {
+    ContainerVT = getContainerForFixedLengthVector(DAG, VT);
+    CastVT = ContainerVT.changeVectorElementType(SrcVT.getVectorElementType());
+    Src = convertToScalableVector(DAG, CastVT, Src);
+  }
----------------
paulwalker-arm wrote:

The lowering for SVE VLS looks to be the wrong way round, which will mean we're likely to use all-active predicates rather than a predicate that matches the fixed vector length.  You'd typically lower the operation to supported common ISD nodes first and then let the lowering for those nodes take care of converting them to use scalable vector types for the bigger than NEON cases.

https://github.com/llvm/llvm-project/pull/89035