[llvm] [AArch64] Improve code generation for experimental.cttz.elts (PR #91505)

[Hari Limaye via llvm-commits]

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@@ -1852,7 +1852,16 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
 }
 
 bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
-  return !Subtarget->hasSVEorSME() || VT != MVT::nxv16i1;
+  // Only SVE and SME architectures support BRKB and CNTP instructions.
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hazzlim wrote:

No worries - Done.

https://github.com/llvm/llvm-project/pull/91505