[llvm] [AArch64] Improve code generation for experimental.cttz.elts (PR #91505)

[David Sherwood via llvm-commits]

================
@@ -1852,7 +1852,16 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
 }
 
 bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
-  return !Subtarget->hasSVEorSME() || VT != MVT::nxv16i1;
+  // Only SVE and SME architectures support BRKB and CNTP instructions.
----------------
david-arm wrote:

nit: The `hasSVEorSME()` check here is mis-leading, since it's not strictly true that having the SME feature automatically means you can use the BRKB and CNTP instructions. We intend to clean this up in future, but for now perhaps it's best to just remove the comment to avoid confusion. Sorry about this!

https://github.com/llvm/llvm-project/pull/91505