[llvm] [AArch64][GlobalISel] Push ADD/SUB through Extend Instructions (PR #90964)

[Matt Arsenault via llvm-commits]

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@@ -554,6 +554,73 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
   MI.eraseFromParent();
 }
 
+// Pushes ADD/SUB through extend instructions to decrease the number of extend
+// instruction at the end by allowing selection of {s|u}addl sooner
+
+// i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
+bool matchPushAddSubExt(
+    MachineInstr &MI, MachineRegisterInfo &MRI,
+    std::tuple<bool, Register, Register, Register> &matchinfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_ADD ||
+         MI.getOpcode() == TargetOpcode::G_SUB &&
+             "Expected a G_ADD or G_SUB instruction\n");
+
+  // Deal with vector types only
+  get<1>(matchinfo) = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(get<1>(matchinfo));
+  if (!DstTy.isVector())
+    return false;
+
+  // Matching instruction pattern
+  Register Src1Reg = MI.getOperand(1).getReg();
+  Register Src2Reg = MI.getOperand(2).getReg();
+  bool ZExt =
+      mi_match(Src1Reg, MRI,
+               m_OneNonDBGUse(m_GZExt(m_Reg(get<2>(matchinfo))))) &&
+      mi_match(Src2Reg, MRI, m_OneNonDBGUse(m_GZExt(m_Reg(get<3>(matchinfo)))));
+  bool SExt =
+      mi_match(Src1Reg, MRI,
+               m_OneNonDBGUse(m_GSExt(m_Reg(get<2>(matchinfo))))) &&
+      mi_match(Src2Reg, MRI, m_OneNonDBGUse(m_GSExt(m_Reg(get<3>(matchinfo)))));
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arsenm wrote:

Can you push this into the tablegen pattern? 

https://github.com/llvm/llvm-project/pull/90964