[llvm] c0b5a96 - [RISCV] Add tests where we could use Zbs instructions in constant materialization. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed May 8 16:05:34 PDT 2024
Author: Craig Topper
Date: 2024-05-08T16:04:54-07:00
New Revision: c0b5a96ac44a70bdc0b138e117e3fea1b49189f5
URL: https://github.com/llvm/llvm-project/commit/c0b5a96ac44a70bdc0b138e117e3fea1b49189f5
DIFF: https://github.com/llvm/llvm-project/commit/c0b5a96ac44a70bdc0b138e117e3fea1b49189f5.diff
LOG: [RISCV] Add tests where we could use Zbs instructions in constant materialization. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/imm.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 9e356a93526cd..6456401dbb865 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -3994,3 +3994,119 @@ define i64 @imm64_same_lo_hi_negative() nounwind {
; RV64-REMAT-NEXT: ret
ret i64 9259542123273814144 ; 0x8080808080808080
}
+
+define i64 @imm64_0x8000080000000() {
+; RV32I-LABEL: imm64_0x8000080000000:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: lui a1, 128
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: imm64_0x8000080000000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: addiw a0, a0, 1
+; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0x8000080000000:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: lui a0, 256
+; RV64IZBA-NEXT: addiw a0, a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 31
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0x8000080000000:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: lui a0, 256
+; RV64IZBB-NEXT: addiw a0, a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 31
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0x8000080000000:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: lui a0, 256
+; RV64IZBS-NEXT: addiw a0, a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 31
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0x8000080000000:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: lui a0, 256
+; RV64IXTHEADBB-NEXT: addiw a0, a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 31
+; RV64IXTHEADBB-NEXT: ret
+;
+; RV32-REMAT-LABEL: imm64_0x8000080000000:
+; RV32-REMAT: # %bb.0:
+; RV32-REMAT-NEXT: lui a0, 524288
+; RV32-REMAT-NEXT: lui a1, 128
+; RV32-REMAT-NEXT: ret
+;
+; RV64-REMAT-LABEL: imm64_0x8000080000000:
+; RV64-REMAT: # %bb.0:
+; RV64-REMAT-NEXT: lui a0, 256
+; RV64-REMAT-NEXT: addiw a0, a0, 1
+; RV64-REMAT-NEXT: slli a0, a0, 31
+; RV64-REMAT-NEXT: ret
+ ret i64 2251801961168896 ; 0x8000080000000
+}
+
+define i64 @imm64_0x10000100000000() {
+; RV32I-LABEL: imm64_0x10000100000000:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 256
+; RV32I-NEXT: addi a1, a1, 1
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: imm64_0x10000100000000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0x10000100000000:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: lui a0, 256
+; RV64IZBA-NEXT: addi a0, a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 32
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0x10000100000000:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: lui a0, 256
+; RV64IZBB-NEXT: addi a0, a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 32
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0x10000100000000:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: lui a0, 256
+; RV64IZBS-NEXT: addi a0, a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 32
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0x10000100000000:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: lui a0, 256
+; RV64IXTHEADBB-NEXT: addi a0, a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 32
+; RV64IXTHEADBB-NEXT: ret
+;
+; RV32-REMAT-LABEL: imm64_0x10000100000000:
+; RV32-REMAT: # %bb.0:
+; RV32-REMAT-NEXT: lui a1, 256
+; RV32-REMAT-NEXT: addi a1, a1, 1
+; RV32-REMAT-NEXT: li a0, 0
+; RV32-REMAT-NEXT: ret
+;
+; RV64-REMAT-LABEL: imm64_0x10000100000000:
+; RV64-REMAT: # %bb.0:
+; RV64-REMAT-NEXT: lui a0, 256
+; RV64-REMAT-NEXT: addi a0, a0, 1
+; RV64-REMAT-NEXT: slli a0, a0, 32
+; RV64-REMAT-NEXT: ret
+ ret i64 4503603922337792 ; 0x10000100000000
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll
index 0ef17ca964db5..c5bb7289e448a 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/imm.ll
@@ -2562,3 +2562,140 @@ define i64 @imm64_same_lo_hi_optsize() nounwind optsize {
; RV64IXTHEADBB-NEXT: ret
ret i64 1157442765409226768 ; 0x0101010101010101
}
+; Hi and lo are the same and also negative.
+define i64 @imm64_same_lo_hi_negative() nounwind {
+; RV64-NOPOOL-LABEL: imm64_same_lo_hi_negative:
+; RV64-NOPOOL: # %bb.0:
+; RV64-NOPOOL-NEXT: lui a0, 983297
+; RV64-NOPOOL-NEXT: slli a0, a0, 4
+; RV64-NOPOOL-NEXT: addi a0, a0, 257
+; RV64-NOPOOL-NEXT: slli a0, a0, 16
+; RV64-NOPOOL-NEXT: addi a0, a0, 257
+; RV64-NOPOOL-NEXT: slli a0, a0, 15
+; RV64-NOPOOL-NEXT: addi a0, a0, 128
+; RV64-NOPOOL-NEXT: ret
+;
+; RV64I-POOL-LABEL: imm64_same_lo_hi_negative:
+; RV64I-POOL: # %bb.0:
+; RV64I-POOL-NEXT: lui a0, %hi(.LCPI65_0)
+; RV64I-POOL-NEXT: ld a0, %lo(.LCPI65_0)(a0)
+; RV64I-POOL-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: lui a0, 526344
+; RV64IZBA-NEXT: addi a0, a0, 128
+; RV64IZBA-NEXT: slli a1, a0, 32
+; RV64IZBA-NEXT: add.uw a0, a0, a1
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: lui a0, 983297
+; RV64IZBB-NEXT: slli a0, a0, 4
+; RV64IZBB-NEXT: addi a0, a0, 257
+; RV64IZBB-NEXT: slli a0, a0, 16
+; RV64IZBB-NEXT: addi a0, a0, 257
+; RV64IZBB-NEXT: slli a0, a0, 15
+; RV64IZBB-NEXT: addi a0, a0, 128
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: lui a0, 983297
+; RV64IZBS-NEXT: slli a0, a0, 4
+; RV64IZBS-NEXT: addi a0, a0, 257
+; RV64IZBS-NEXT: slli a0, a0, 16
+; RV64IZBS-NEXT: addi a0, a0, 257
+; RV64IZBS-NEXT: slli a0, a0, 15
+; RV64IZBS-NEXT: addi a0, a0, 128
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_same_lo_hi_negative:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: lui a0, 983297
+; RV64IXTHEADBB-NEXT: slli a0, a0, 4
+; RV64IXTHEADBB-NEXT: addi a0, a0, 257
+; RV64IXTHEADBB-NEXT: slli a0, a0, 16
+; RV64IXTHEADBB-NEXT: addi a0, a0, 257
+; RV64IXTHEADBB-NEXT: slli a0, a0, 15
+; RV64IXTHEADBB-NEXT: addi a0, a0, 128
+; RV64IXTHEADBB-NEXT: ret
+ ret i64 9259542123273814144 ; 0x8080808080808080
+}
+
+define i64 @imm64_0x8000080000000() {
+; RV64I-LABEL: imm64_0x8000080000000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: addiw a0, a0, 1
+; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0x8000080000000:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: lui a0, 256
+; RV64IZBA-NEXT: addiw a0, a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 31
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0x8000080000000:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: lui a0, 256
+; RV64IZBB-NEXT: addiw a0, a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 31
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0x8000080000000:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: lui a0, 256
+; RV64IZBS-NEXT: addiw a0, a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 31
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0x8000080000000:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: lui a0, 256
+; RV64IXTHEADBB-NEXT: addiw a0, a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 31
+; RV64IXTHEADBB-NEXT: ret
+ ret i64 2251801961168896 ; 0x8000080000000
+}
+
+define i64 @imm64_0x10000100000000() {
+; RV64I-LABEL: imm64_0x10000100000000:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 256
+; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64IZBA-LABEL: imm64_0x10000100000000:
+; RV64IZBA: # %bb.0:
+; RV64IZBA-NEXT: lui a0, 256
+; RV64IZBA-NEXT: addi a0, a0, 1
+; RV64IZBA-NEXT: slli a0, a0, 32
+; RV64IZBA-NEXT: ret
+;
+; RV64IZBB-LABEL: imm64_0x10000100000000:
+; RV64IZBB: # %bb.0:
+; RV64IZBB-NEXT: lui a0, 256
+; RV64IZBB-NEXT: addi a0, a0, 1
+; RV64IZBB-NEXT: slli a0, a0, 32
+; RV64IZBB-NEXT: ret
+;
+; RV64IZBS-LABEL: imm64_0x10000100000000:
+; RV64IZBS: # %bb.0:
+; RV64IZBS-NEXT: lui a0, 256
+; RV64IZBS-NEXT: addi a0, a0, 1
+; RV64IZBS-NEXT: slli a0, a0, 32
+; RV64IZBS-NEXT: ret
+;
+; RV64IXTHEADBB-LABEL: imm64_0x10000100000000:
+; RV64IXTHEADBB: # %bb.0:
+; RV64IXTHEADBB-NEXT: lui a0, 256
+; RV64IXTHEADBB-NEXT: addi a0, a0, 1
+; RV64IXTHEADBB-NEXT: slli a0, a0, 32
+; RV64IXTHEADBB-NEXT: ret
+ ret i64 4503603922337792 ; 0x10000100000000
+}
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