[llvm] promote Pseduo Opcode from 32bit to 64bits after eliminating the `extsw` instruction in PPCMIPeepholes optimization (PR #85451)

[Kamau Bridgeman via llvm-commits]

================
@@ -1050,7 +1050,16 @@ bool PPCMIPeephole::simplifyCode() {
         } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
                    TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
-          // sign-extended.
+          // sign-extended. but we are not sure whether a spill will occur
+          // during register allocation. All these instructions in the chain
+          // used to deduce sign extension to eliminate the 'extsw' will need to
+          // be promoted to 64-bit pseudo instructions when the 'extsw' is
+          // eliminated. If there is no promotion, it will use the 'stw' instead
+          // of 'std', and 'lwz' instead of 'ld' when spilling, since the
+          // register class is 32-bits. Consequently, the high 32-bit
+          // information will be lost.
----------------
kamaub wrote:

It might flow nicer if we put the what will happen if we don't promote first and then say how we promote after.

https://github.com/llvm/llvm-project/pull/85451