[llvm] promote Pseduo Opcode from 32bit to 64bits after eliminating the `extsw` instruction in PPCMIPeepholes optimization (PR #85451)

[Kamau Bridgeman via llvm-commits]

================
@@ -5234,6 +5234,244 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
 const unsigned MAX_BINOP_DEPTH = 1;
+
+// The `PromoteInstr32To64ForEmliEXTSW` function is recursive. The parameter
+// BinOpDepth  does not count all of the recursions. The parameter BinOpDepth is
+// incremented  only when `PromoteInstr32To64ForEmliEXTSW` calls itself more
+// than once. This is done to prevent exponential recursion. The function will
+// promote the instruction which defines the register `Reg` in the parameter
+// from a 32-bit to a 64-bit instruction if needed. Additionally, all the used
+// and defined registers in the instruction may also need to be promoted from
+// 32-bit to 64-bit based on the promoted instruction description. If a used
----------------
kamaub wrote:

We should mention the tablegen flag used to map PPC instructions and the opcodes defined by the `issignorzeroextended()`.

https://github.com/llvm/llvm-project/pull/85451