[llvm] ISel/AArch64/SVE: custom lower vector ISD::[L]LRINT (PR #89035)

[David Green via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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davemgreen wrote:

Most of the fixed-length SVE tests use -aarch64-sve-vector-bits-min=256 (or higher) to test vscales > 1.

https://github.com/llvm/llvm-project/pull/89035