[llvm] [InstCombine] Transform high latency, dependent FSQRT/FDIV into FMUL (PR #87474)

[Matt Arsenault via llvm-commits]

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@@ -626,6 +626,89 @@ Instruction *InstCombinerImpl::foldPowiReassoc(BinaryOperator &I) {
   return nullptr;
 }
 
+// Check legality for transforming
+// x = 1.0/sqrt(a)
+// r1 = x * x;
+// r2 = a/sqrt(a);
+//
+// TO
+//
+// r1 = 1/a
+// r2 = sqrt(a)
+// x = r1 * r2
+static bool isFSqrtDivToFMulLegal(Instruction *X,
+                                  const SmallVectorImpl<Instruction *> &R1,
+                                  const SmallVectorImpl<Instruction *> &R2) {
+  BasicBlock *BBx = X->getParent();
+  BasicBlock *BBr1 = R1[0]->getParent();
+  BasicBlock *BBr2 = R2[0]->getParent();
+
+  CallInst *FSqrt = cast<CallInst>(X->getOperand(1));
+  if (!(FSqrt->hasAllowReassoc() && FSqrt->hasNoNaNs() &&
+        FSqrt->hasNoSignedZeros() && FSqrt->hasNoInfs()))
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arsenm wrote:

deMorgan this condition 

https://github.com/llvm/llvm-project/pull/87474