[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

BeMg wrote:

Summary Update so far.

There are two patch try to achieve similar job - move the vsetvli pass after vector register allocation.

Both patches:
- Use VNInfo to store AVLReg information inside VSETVLInfo instead of MachineInstr
- Utilize LiveIntervals to find the definition instead of MRI.getVRegDef
- Can use a command-line flag to switch between pre-register allocation (pre-RA) and post-RA modes
- Allow the vsetvli pass to execute without considering the SSA form (in most cases)

The major differences between them:

- https://github.com/llvm/llvm-project/pull/70549
  - `needVSETVLIPHI` function keep both pre-RA and post-RA path (The isPHIdef() doesn't exist when still SSA)
  - Preserves the pre-RA pass without moving in codegen pipeline
- https://github.com/llvm/llvm-project/pull/91440
  - Shares the entire pass between pre-RA and post-RA modes
  - Requires moving the pre-RA pass after `PHI Elimination` or `RegisterCoalescer`


https://github.com/llvm/llvm-project/pull/70549