[llvm] [TableGen] Fix regunit superset calculation (PR #81850)

[Jay Foad via llvm-commits]

jayfoad wrote:

> Do you have an example of a diff of the `.inc` file generated before and after this patch?

https://github.com/jayfoad/llvm-generated/commit/547ef8c2e6eff9e37122e797ad5acdb5e8eb4180#diff-54007a1ac1ec6e07cbf61a38f863ea3b1e8064558ab29655338ece8b7299acbd

This is all related to how `CodeGenRegBank::pruneUnitSets` works. I'd love to hear any insights into why it does what it does. It says it finds equivalence classes of UnitSets, but the "equivalence" relation includes sets that differ by one or two regunits, which is not even transitive.

The comment on `pruneUnitSets` says:
```
/// Ideally we could fix this statically in
/// tablegen by (1) having the target define register classes that only include
/// the allocatable registers and marking other classes as non-allocatable and
/// (2) having a way to mark special purpose classes as "don't-care" classes for
/// the purpose of pressure.
```
Is that still a realistic way forward, and would it allow us to remove this pruning code?

https://github.com/llvm/llvm-project/pull/81850