[llvm] [RISCV] Optimize pattern `(setcc (selectLT (vfirst_vl ...) , 0, EVL, ...), EVL)` (PR #90538)

[Craig Topper via llvm-commits]

================
@@ -13678,9 +13687,107 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   EVT VT = N->getValueType(0);
   EVT OpVT = N0.getValueType();
+  SDLoc DL(N);
+
+  // Both rules are looking for an equality compare.
+  if (!isIntEqualitySetCC(Cond))
+    return SDValue();
+
+  // Rule 1
+  using namespace SDPatternMatch;
+  auto matchSelectCC = [](SDValue Op, SDValue VLCandidate, bool Inverse,
+                          SDValue &Select) -> bool {
+    SDValue VLCandVTNode;
+    EVT VLCandVT = VLCandidate.getValueType();
+    // Remove any sext.
+    if (sd_match(Op, m_Opc(ISD::SIGN_EXTEND_INREG)))
----------------
topperc wrote:

The sign extend wasn't created by the intrinsic. It was likely created by type legalization, but that's not the only way it can be created. So we can't assume the type in sign_extend_inreg represents the original type of the intrinsic.

I'm not even sure how to implement this combine to handle all the cases we need to handle. You'll probably get different results if you add the `zeroext` attribute to the EVL function argument in your test. That would remove the AND between the EVL and the vfirst, but it would not remove the sign_extend_inreg between the evl and the compare.

https://github.com/llvm/llvm-project/pull/90538