[llvm] a70ad96 - [AMDGPU] Fix condition in VOP3_Real_Base. NFCI. (#91373)

[via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2024-05-07T13:45:58-07:00
New Revision: a70ad96b3cc5275246f7f007d1892bb867b75bc0

URL: https://github.com/llvm/llvm-project/commit/a70ad96b3cc5275246f7f007d1892bb867b75bc0
DIFF: https://github.com/llvm/llvm-project/commit/a70ad96b3cc5275246f7f007d1892bb867b75bc0.diff

LOG: [AMDGPU] Fix condition in VOP3_Real_Base. NFCI. (#91373)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOPInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 74988ac634c3..d974aacd7d45 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1410,7 +1410,7 @@ multiclass VOP3_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
       def _e64#Gen.Suffix :
         VOP3_Real_Gen<ps, Gen>,
         VOP3FP8OpSel_dst_bytesel_gfx11_gfx12<op, ps.Pfl>;
-    } if ps.Pfl.HasOpSel then {
+    } else if ps.Pfl.HasOpSel then {
       def _e64#Gen.Suffix :
         VOP3_Real_Gen<ps, Gen>,
         VOP3OpSel_gfx11_gfx12<op, ps.Pfl>;