[llvm] 63ceb9a - [X86] sext-subreg.ll - regenerate checks

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-05-07T17:27:58+01:00
New Revision: 63ceb9afc693209964efd4ac4844c9c0712c312d

URL: https://github.com/llvm/llvm-project/commit/63ceb9afc693209964efd4ac4844c9c0712c312d
DIFF: https://github.com/llvm/llvm-project/commit/63ceb9afc693209964efd4ac4844c9c0712c312d.diff

LOG: [X86] sext-subreg.ll - regenerate checks

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/sext-subreg.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/sext-subreg.ll b/llvm/test/CodeGen/X86/sext-subreg.ll
index 3e54f24d13affe..20451ff208cc05 100644
--- a/llvm/test/CodeGen/X86/sext-subreg.ll
+++ b/llvm/test/CodeGen/X86/sext-subreg.ll
@@ -1,16 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 ; rdar://7529457
 
 define i64 @t(i64 %A, i64 %B, ptr %P, ptr%P2) nounwind {
 ; CHECK-LABEL: t:
-; CHECK: movslq %e{{.*}}, %rax
-; CHECK: movq %rax
-; CHECK: movl %eax
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addq %rsi, %rdi
+; CHECK-NEXT:    movl %edi, (%rdx)
+; CHECK-NEXT:    movslq %edi, %rax
+; CHECK-NEXT:    movq %rax, (%rcx)
+; CHECK-NEXT:    movl %eax, (%rdx)
+; CHECK-NEXT:    retq
   %C = add i64 %A, %B
   %D = trunc i64 %C to i32
   store volatile i32 %D, ptr %P
   %E = shl i64 %C, 32
-  %F = ashr i64 %E, 32  
+  %F = ashr i64 %E, 32
   store volatile i64 %F, ptr%P2
   store volatile i32 %D, ptr %P
   ret i64 undef