[llvm] f00f294 - [SLP]Fix PR91309: Do not consider SExt as always producing signed result.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-05-07T08:57:52-07:00
New Revision: f00f2941307e04d3b7320969ee3fec9af31246ba

URL: https://github.com/llvm/llvm-project/commit/f00f2941307e04d3b7320969ee3fec9af31246ba
DIFF: https://github.com/llvm/llvm-project/commit/f00f2941307e04d3b7320969ee3fec9af31246ba.diff

LOG: [SLP]Fix PR91309: Do not consider SExt as always producing signed result.

Still need to do the full analysis of the signedness of the values
rather than rely on Instruction opcode, if the opcode is SExt. Still may
produce unsigned result.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index d6a2273d0f185..98561f9ca0442 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -15487,8 +15487,7 @@ void BoUpSLP::computeMinimumValueSizes() {
       TreeEntry *TE = VectorizableTree[Idx].get();
       if (MinBWs.contains(TE))
         continue;
-      bool IsSigned = TE->getOpcode() == Instruction::SExt ||
-                      any_of(TE->Scalars, [&](Value *R) {
+      bool IsSigned = any_of(TE->Scalars, [&](Value *R) {
                         return !isKnownNonNegative(R, SimplifyQuery(*DL));
                       });
       MinBWs.try_emplace(TE, MaxBitWidth, IsSigned);

diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll
index 406e5b9b930dc..96ed3e77d9877 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll
@@ -4,10 +4,10 @@
 define i16 @test()  {
 ; CHECK-LABEL: define i16 @test() {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[LNOT_EXT:%.*]] = zext i1 [[LNOT]] to i16
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i16 0, [[LNOT_EXT]]
-; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 true, true
 ; CHECK-NEXT:    [[LNOT_EXT6:%.*]] = zext i1 [[LNOT5]] to i16
 ; CHECK-NEXT:    [[ADD7:%.*]] = add nsw i16 [[ADD]], [[LNOT_EXT6]]
 ; CHECK-NEXT:    ret i16 [[ADD7]]