[llvm] [InstCombine] Propogate disjoint flags during shl-binop transform (PR #91333)
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Tue May 7 07:08:18 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: AtariDreams (AtariDreams)
<details>
<summary>Changes</summary>
Proof: https://alive2.llvm.org/ce/z/7YWJ69
---
Full diff: https://github.com/llvm/llvm-project/pull/91333.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp (+52-3)
- (modified) llvm/test/Transforms/InstCombine/shl-bo.ll (+19-2)
``````````diff
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 1cb21a1d81af4b..de08850355e664 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1159,6 +1159,9 @@ Instruction *InstCombinerImpl::visitShl(BinaryOperator &I) {
// (X bop (Y << C))
Value *B =
Builder.CreateBinOp(Op0BO->getOpcode(), X, YS, Shr->getName());
+ if (auto *Disjoint = dyn_cast<PossiblyDisjointInst>(Op0BO);
+ Disjoint && Disjoint->isDisjoint())
+ cast<PossiblyDisjointInst>(B)->setIsDisjoint(true);
unsigned Op1Val = C->getLimitedValue(BitWidth);
APInt Bits = APInt::getHighBitsSet(BitWidth, BitWidth - Op1Val);
Constant *Mask = ConstantInt::get(Ty, Bits);
@@ -1174,7 +1177,11 @@ Instruction *InstCombinerImpl::visitShl(BinaryOperator &I) {
// X & (CC << C)
Value *M = Builder.CreateAnd(X, ConstantInt::get(Ty, CC->shl(*C)),
X->getName() + ".mask");
- return BinaryOperator::Create(Op0BO->getOpcode(), M, YS);
+ auto *NewOp = BinaryOperator::Create(Op0BO->getOpcode(), M, YS);
+ if (auto *Disjoint = dyn_cast<PossiblyDisjointInst>(Op0BO);
+ Disjoint && Disjoint->isDisjoint())
+ cast<PossiblyDisjointInst>(NewOp)->setIsDisjoint(true);
+ return NewOp;
}
}
@@ -1259,6 +1266,50 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
match(Op1, m_SpecificIntAllowPoison(BitWidth - 1)))
return new ZExtInst(Builder.CreateIsNotNeg(X, "isnotneg"), Ty);
+ Value *Y;
+ if (match(Op0, m_OneUse(m_NUWSub(m_NUWShl(m_Value(X), m_Specific(Op1)),
+ m_Value(Y))))) {
+ Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
+ auto *NewSub = BinaryOperator::CreateNUWSub(NewLshr, X);
+ NewSub->setHasNoSignedWrap(
+ cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ return NewSub;
+ }
+
+ auto isSuitableBinOpcode = [](Instruction::BinaryOps BinOpcode) {
+ switch (BinOpcode) {
+ default:
+ return false;
+ case Instruction::Add:
+ case Instruction::Or:
+ case Instruction::Xor:
+ // And does not work here, and sub is handled separately.
+ return true;
+ }
+ };
+
+ // If both the add and the shift are nuw, then:
+ // ((X << nuw Z) binop nuw Y) >>u Z --> X binop nuw (Y >>u Z)
+ if (match(Op0, m_OneUse(m_c_BinOp(m_NUWShl(m_Value(X), m_Specific(Op1)),
+ m_Value(Y))))) {
+ BinaryOperator *Op0OB = cast<BinaryOperator>(Op0);
+ if (isSuitableBinOpcode(Op0OB->getOpcode())) {
+ if (auto *OBO = dyn_cast<OverflowingBinaryOperator>(Op0);
+ !OBO || OBO->hasNoUnsignedWrap()) {
+ Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
+ auto *NewBinOp = BinaryOperator::Create(Op0OB->getOpcode(), NewLshr, X);
+ if (OBO) {
+ NewBinOp->setHasNoUnsignedWrap(true);
+ NewBinOp->setHasNoSignedWrap(OBO->hasNoSignedWrap());
+ } else if (auto *Disjoint = dyn_cast<PossiblyDisjointInst>(Op0);
+ Disjoint && Disjoint->isDisjoint()) {
+ cast<PossiblyDisjointInst>(NewBinOp)->setIsDisjoint(true);
+ }
+ return NewBinOp;
+ }
+ }
+ }
+
if (match(Op1, m_APInt(C))) {
unsigned ShAmtC = C->getZExtValue();
auto *II = dyn_cast<IntrinsicInst>(Op0);
@@ -1275,7 +1326,6 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return new ZExtInst(Cmp, Ty);
}
- Value *X;
const APInt *C1;
if (match(Op0, m_Shl(m_Value(X), m_APInt(C1))) && C1->ult(BitWidth)) {
if (C1->ult(ShAmtC)) {
@@ -1320,7 +1370,6 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
// ((X << C) + Y) >>u C --> (X + (Y >>u C)) & (-1 >>u C)
// TODO: Consolidate with the more general transform that starts from shl
// (the shifts are in the opposite order).
- Value *Y;
if (match(Op0,
m_OneUse(m_c_Add(m_OneUse(m_Shl(m_Value(X), m_Specific(Op1))),
m_Value(Y))))) {
diff --git a/llvm/test/Transforms/InstCombine/shl-bo.ll b/llvm/test/Transforms/InstCombine/shl-bo.ll
index d33d27c912d6be..ff78dcc708d630 100644
--- a/llvm/test/Transforms/InstCombine/shl-bo.ll
+++ b/llvm/test/Transforms/InstCombine/shl-bo.ll
@@ -294,6 +294,23 @@ define i8 @lshr_and_or(i8 %a, i8 %y) {
ret i8 %l
}
+define i8 @lshr_and_or_disjoint(i8 %a, i8 %y) {
+; CHECK-LABEL: @lshr_and_or_disjoint(
+; CHECK-NEXT: [[X:%.*]] = srem i8 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = shl i8 [[X]], 2
+; CHECK-NEXT: [[Y_MASK:%.*]] = and i8 [[Y:%.*]], 52
+; CHECK-NEXT: [[L:%.*]] = or disjoint i8 [[Y_MASK]], [[B1]]
+; CHECK-NEXT: ret i8 [[L]]
+;
+ %x = srem i8 %a, 42 ; thwart complexity-based canonicalization
+ %r = lshr i8 %y, 2
+ %m = and i8 %r, 13
+ %b = or disjoint i8 %x, %m
+ %l = shl i8 %b, 2
+ ret i8 %l
+}
+
+
define <2 x i8> @lshr_and_or_commute_splat(<2 x i8> %a, <2 x i8> %y) {
; CHECK-LABEL: @lshr_and_or_commute_splat(
; CHECK-NEXT: [[X:%.*]] = srem <2 x i8> [[A:%.*]], <i8 42, i8 42>
@@ -614,8 +631,8 @@ define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) {
define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) {
; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <16 x i8> [[IN0:%.*]], <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
-; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[TMP1]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32>
+; CHECK-NEXT: [[VSRA_N2:%.*]] = mul <16 x i8> [[IN0:%.*]], <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
+; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[VSRA_N2]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32>
; CHECK-NEXT: ret <16 x i8> [[VSHL_N]]
;
%vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
``````````
</details>
https://github.com/llvm/llvm-project/pull/91333
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