[llvm] 5d9b549 - [SLP][NFC]Add a test showing incorrect signedness detection in sext nodes.

Alexey Bataev via llvm-commits llvm-commits at lists.llvm.org
Tue May 7 06:46:47 PDT 2024


Author: Alexey Bataev
Date: 2024-05-07T06:46:30-07:00
New Revision: 5d9b549bb05ad31727cd019bcefeae7b94b2dbd2

URL: https://github.com/llvm/llvm-project/commit/5d9b549bb05ad31727cd019bcefeae7b94b2dbd2
DIFF: https://github.com/llvm/llvm-project/commit/5d9b549bb05ad31727cd019bcefeae7b94b2dbd2.diff

LOG: [SLP][NFC]Add a test showing incorrect signedness detection in sext nodes.

Added: 
    llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll
new file mode 100644
index 00000000000000..406e5b9b930dcc
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=aarch64 -passes=slp-vectorizer -S -slp-threshold=-100 < %s | FileCheck %s
+
+define i16 @test()  {
+; CHECK-LABEL: define i16 @test() {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT_EXT:%.*]] = zext i1 [[LNOT]] to i16
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i16 0, [[LNOT_EXT]]
+; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 false, true
+; CHECK-NEXT:    [[LNOT_EXT6:%.*]] = zext i1 [[LNOT5]] to i16
+; CHECK-NEXT:    [[ADD7:%.*]] = add nsw i16 [[ADD]], [[LNOT_EXT6]]
+; CHECK-NEXT:    ret i16 [[ADD7]]
+;
+entry:
+  %conv = sext i16 1 to i32
+  %cmp = icmp eq i32 %conv, 1
+  %lnot = xor i1 %cmp, true
+  %lnot.ext = zext i1 %lnot to i16
+  %add = add nsw i16 0, %lnot.ext
+  %conv2 = sext i16 1 to i32
+  %cmp3 = icmp eq i32 %conv2, 1
+  %lnot5 = xor i1 %cmp3, true
+  %lnot.ext6 = zext i1 %lnot5 to i16
+  %add7 = add nsw i16 %add, %lnot.ext6
+  ret i16 %add7
+}


        


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