[llvm] DAG: Skip 0 sign handling in minimum/maximum lowering for _ieee case (PR #91326)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 7 06:33:53 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
dc9664a8adae17f2083fbcc8e96cfce606c56d57 changed the documentation to assume these order -0 as less than +0.
---
Patch is 498.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/91326.diff
8 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+8-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll (+625-2813)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll (+30-237)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll (+77-407)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll (+407-2193)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll (+30-237)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll (+77-407)
- (modified) llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll (+32-208)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 336d89fbcf638..7dc5b386e17c6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8400,8 +8400,14 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
SDValue MinMax;
unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM;
+
+ // FIXME: We should probably define fminnum/fmaxnum variants with correct
+ // signed zero behavior.
+ bool MinMaxMustRespectOrderedZero = false;
+
if (isOperationLegalOrCustom(CompOpcIeee, VT)) {
MinMax = DAG.getNode(CompOpcIeee, DL, VT, LHS, RHS);
+ MinMaxMustRespectOrderedZero = true;
} else if (isOperationLegalOrCustom(CompOpc, VT)) {
MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS);
} else {
@@ -8421,8 +8427,8 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
}
// fminimum/fmaximum requires -0.0 less than +0.0
- if (!N->getFlags().hasNoSignedZeros() && !DAG.isKnownNeverZeroFloat(RHS) &&
- !DAG.isKnownNeverZeroFloat(LHS)) {
+ if (!MinMaxMustRespectOrderedZero && !N->getFlags().hasNoSignedZeros() &&
+ !DAG.isKnownNeverZeroFloat(RHS) && !DAG.isKnownNeverZeroFloat(LHS)) {
SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
SDValue TestZero =
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index c49e6a9a9f25c..d8524c8a20683 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -18,13 +18,7 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f16:
@@ -33,13 +27,7 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX8-NEXT: v_max_f16_e32 v2, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f16:
@@ -48,13 +36,7 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f16:
@@ -64,16 +46,7 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f16:
@@ -81,13 +54,7 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f16:
@@ -95,15 +62,8 @@ define half @v_maximum_f16(half %src0, half %src1) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f16:
@@ -127,78 +87,37 @@ define half @v_maximum_f16__nnan(half %src0, half %src1) {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT: v_max_f32_e32 v2, v0, v1
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_max_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f16__nnan:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f16__nnan:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f16__nnan:
; GFX940: ; %bb.0:
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX940-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX940-NEXT: v_max_f16_e32 v0, v0, v1
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f16__nnan:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-NEXT: v_max_f16_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f16__nnan:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: v_max_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f16__nnan:
@@ -352,13 +271,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX7-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f16__nnan_src0:
@@ -368,13 +281,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX8-NEXT: v_max_f16_e32 v2, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f16__nnan_src0:
@@ -384,13 +291,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f16__nnan_src0:
@@ -401,16 +302,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f16__nnan_src0:
@@ -419,13 +311,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX10-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f16__nnan_src0:
@@ -435,15 +321,7 @@ define half @v_maximum_f16__nnan_src0(half %arg0, half %src1) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f16__nnan_src0:
@@ -474,13 +352,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX7-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX7-NEXT: v_max_f32_e32 v3, v0, v1
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f16__nnan_src1:
@@ -490,13 +362,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX8-NEXT: v_max_f16_e32 v2, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f16__nnan_src1:
@@ -506,13 +372,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX9-NEXT: v_max_f16_e32 v2, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX9-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX9-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f16__nnan_src1:
@@ -523,16 +383,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX940-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX940-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v0, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX940-NEXT: v_cmp_class_f16_e64 vcc, v1, 64
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX940-NEXT: v_cmp_eq_f16_e32 vcc, 0, v2
-; GFX940-NEXT: s_nop 1
-; GFX940-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX940-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f16__nnan_src1:
@@ -541,13 +392,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX10-NEXT: v_add_f16_e32 v1, 1.0, v1
; GFX10-NEXT: v_max_f16_e32 v2, v0, v1
; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX10-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f16__nnan_src1:
@@ -557,15 +402,7 @@ define half @v_maximum_f16__nnan_src1(half %src0, half %arg1) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_max_f16_e32 v2, v0, v1
; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 0x7e00, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v0, 64
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT: v_cmp_class_f16_e64 vcc_lo, v1, 64
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f16__nnan_src1:
@@ -595,13 +432,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) {
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_max_f32_e32 v3, v1, v0
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v1, v0
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v1, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX7-NEXT: v_cmp_class_f32_e64 vcc, v0, 64
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX7-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use v0
@@ -615,14 +446,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) {
; GFX8-NEXT: v_max_f16_e32 v1, s4, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX8-NEXT: v_cmp_o_f16_e32 vcc, s4, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s4, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
-; GFX8-NEXT: v_cmp_class_f16_e64 vcc, s5, 64
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-NEXT: v_cmp_eq_f16_e32 vcc, 0, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v0
@@ -636,14 +460,7 @@ define void @s_maximum_f16(half inre...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/91326
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