[llvm] [AArch64][GlobalISel] Push ADD/SUB through Extend Instructions (PR #90964)

[Amara Emerson via llvm-commits]

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@@ -554,6 +554,74 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
   MI.eraseFromParent();
 }
 
+// Pushes ADD/SUB through extend instructions to decrease the number of extend
+// instruction at the end by allowing selection of {s|u}addl sooner
+
+// i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
+bool matchPushAddSubExt(
+    MachineInstr &MI, MachineRegisterInfo &MRI,
+    std::tuple<bool, Register, Register, Register> &matchinfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_ADD ||
+         MI.getOpcode() == TargetOpcode::G_SUB &&
+             "Expected a G_ADD or G_SUB instruction\n");
+  MachineInstr *ExtMI1 = MRI.getVRegDef(MI.getOperand(1).getReg());
+  MachineInstr *ExtMI2 = MRI.getVRegDef(MI.getOperand(2).getReg());
+
+  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+  if (!DstTy.isVector())
+    return false;
+
+  // Check the source came from G_{S/Z}EXT instructions
+  if (ExtMI1->getOpcode() != ExtMI2->getOpcode() ||
+      (ExtMI1->getOpcode() != TargetOpcode::G_SEXT &&
+       ExtMI1->getOpcode() != TargetOpcode::G_ZEXT))
+    return false;
+
+  if (!MRI.hasOneUse(ExtMI1->getOperand(0).getReg()) ||
+      !MRI.hasOneUse(ExtMI2->getOperand(0).getReg()))
+    return false;
+
+  // Return true if G_{S|Z}EXT instruction is more than 2* source
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aemerson wrote:

Could you use MIPattern for these?

https://github.com/llvm/llvm-project/pull/90964