[llvm] d584df6 - [SLP][NFC]Add a test with incorrect smin analysis for minimal bitwidth, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-05-06T07:46:41-07:00
New Revision: d584df6c8fd4f1a517fa7373d43e9ba2cb10f47f

URL: https://github.com/llvm/llvm-project/commit/d584df6c8fd4f1a517fa7373d43e9ba2cb10f47f
DIFF: https://github.com/llvm/llvm-project/commit/d584df6c8fd4f1a517fa7373d43e9ba2cb10f47f.diff

LOG: [SLP][NFC]Add a test with incorrect smin analysis for minimal bitwidth, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
new file mode 100644
index 00000000000000..41517b94accf1a
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S -passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s
+
+define <4 x i32> @test(i16 %0, i16 %1) {
+; CHECK-LABEL: define <4 x i32> @test(
+; CHECK-SAME: i16 [[TMP0:%.*]], i16 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i16> <i16 poison, i16 0>, i16 [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
+; CHECK-NEXT:    [[CONV15_I:%.*]] = sext i16 [[TMP0]] to i32
+; CHECK-NEXT:    [[TMP4:%.*]] = xor <4 x i16> [[TMP3]], <i16 -1, i16 -1, i16 -1, i16 -1>
+; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[CONV15_I]] to i16
+; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 poison, i16 poison>, i16 [[TMP5]], i32 1
+; CHECK-NEXT:    [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[TMP8:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP4]], <4 x i16> [[TMP7]])
+; CHECK-NEXT:    [[TMP9:%.*]] = zext <4 x i16> [[TMP8]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP9]]
+;
+entry:
+  %conv13.1.i = zext i16 %1 to i32
+  %not.i = xor i32 %conv13.1.i, -1
+  %cond19.i = tail call i32 @llvm.smax.i32(i32 %not.i, i32 0)
+  %conv21.i = and i32 %cond19.i, 65535
+  %not.1.i = xor i32 %conv13.1.i, -1
+  %conv15.i = sext i16 %0 to i32
+  %cond19.1.i = tail call i32 @llvm.smax.i32(i32 %not.1.i, i32 %conv15.i)
+  %conv21.1.i = and i32 %cond19.1.i, 65535
+  %not.2.i = xor i32 %conv13.1.i, -1
+  %cond19.2.i = tail call i32 @llvm.smax.i32(i32 %not.2.i, i32 %conv15.i)
+  %conv21.2.i = and i32 %cond19.2.i, 65535
+  %conv13.3.i = zext i16 0 to i32
+  %not.3.i = xor i32 %conv13.3.i, -1
+  %cond19.3.i = tail call i32 @llvm.smax.i32(i32 %not.3.i, i32 %conv15.i)
+  %conv21.3.i = and i32 %cond19.3.i, 65535
+  %ins1 = insertelement <4 x i32> poison, i32 %conv21.i, i32 0
+  %ins2 = insertelement <4 x i32> %ins1, i32 %conv21.1.i, i32 1
+  %ins3 = insertelement <4 x i32> %ins2, i32 %conv21.2.i, i32 2
+  %ins4 = insertelement <4 x i32> %ins3, i32 %conv21.3.i, i32 3
+  ret <4 x i32> %ins4
+}