[llvm] [RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (PR #90636)

[Piyou Chen via llvm-commits]

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@@ -89,8 +96,8 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
           LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
           continue;
         }
+        LIS.removeInterval(Reg);
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BeMg wrote:

nit: maybe could add `if(LIS.hasInterval(Reg))` or `assert(LIS.hasInterval(Reg))` to make sure the VReg has intervals. 

https://github.com/llvm/llvm-project/pull/90636