[llvm] [TII][NFC] Add renamable bit to copyPhysReg (PR #91179)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 6 02:50:40 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: Piyou Chen (BeMg)
<details>
<summary>Changes</summary>
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case.
This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
---
Patch is 46.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/91179.diff
57 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+3-2)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/R600InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/R600InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/ARC/ARCInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/ARC/ARCInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/ARM/Thumb1InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/ARM/Thumb1InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/AVR/AVRInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/AVR/AVRInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/BPF/BPFInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/BPF/BPFInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/CSKY/CSKYInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/CSKY/CSKYInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Lanai/LanaiInstrInfo.cpp (+2-2)
- (modified) llvm/lib/Target/Lanai/LanaiInstrInfo.h (+3-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/MSP430/MSP430InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/MSP430/MSP430InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Mips/Mips16InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/Mips/Mips16InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/VE/VEInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/VE/VEInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp (+3-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/X86/X86InstrInfo.h (+2-1)
- (modified) llvm/lib/Target/XCore/XCoreInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/XCore/XCoreInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp (+2-1)
- (modified) llvm/lib/Target/Xtensa/XtensaInstrInfo.h (+2-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index d5b1df2114e9e7..928b4c452779f0 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -995,8 +995,9 @@ class TargetInstrInfo : public MCInstrInfo {
/// large registers. See for example the ARM target.
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
- MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const {
+ MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest = false,
+ bool RenamableSrc = false) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 55fecc4b4845fd..d328012bbe4b6e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4419,7 +4419,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
if (AArch64::GPR32spRegClass.contains(DestReg) &&
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
const TargetRegisterInfo *TRI = &getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index f434799c3982b4..5d0355e3f23112 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -335,7 +335,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
llvm::ArrayRef<unsigned> Indices) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 98e7359357891a..73c0561794653e 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned VectorComponents = 0;
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index f720e4656348c8..c767ecb24590b3 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 6599d0abd135cd..0cdbe15d234b7c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -797,7 +797,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
unsigned Size = RI.getRegSizeInBits(*RC);
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 84bb73cc9a796a..536a235a961a15 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -255,7 +255,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 9b5e45cb5fe974..78db68fca3050a 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
assert(ARC::GPR32RegClass.contains(SrcReg) &&
"Only GPR32 src copy supported.");
assert(ARC::GPR32RegClass.contains(DestReg) &&
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index 1875aafbde8261..e25f9902522607 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 8f873bee484acc..3bd22f493f6220 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -891,7 +891,9 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index a3c2684ac1fb97..2ae00dc18c4fcb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -209,7 +209,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 5b0b799880a35f..dc337237b89c91 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -41,7 +41,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Need to check the arch.
MachineFunction &MF = *MBB.getParent();
const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 984bec4e64490b..84241fb8a9a66b 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -39,7 +39,8 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 8ef5c3d9d6bad3..7908ed42a57131 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -150,7 +150,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Handle SPR, DPR, and QPR copies.
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 8915da8c5bf3c8..70ee3270e64ac9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -39,7 +39,8 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index 18b7365fc5aa0f..7b0f8d74e77c2f 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -42,7 +42,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
unsigned Opc;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 28c0e0319d46ed..8eb4292f2422d2 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -75,7 +75,8 @@ class AVRInstrInfo : public AVRGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index 2209f1f1462b43..1b07e7ffc0d313 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -31,7 +31,8 @@ BPFInstrInfo::BPFInstrInfo()
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index 354aca1bd2f93b..a6b6fd7dc4d96f 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -31,7 +31,8 @@ class BPFInstrInfo : public BPFGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index 6baca84ab3d0a6..a2bb87bcaaf942 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -478,7 +478,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
if (CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::CARRYRegClass.contains(DestReg)) {
if (STI.hasE2()) {
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index 4e3866b1188ca0..54c1106310d856 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -55,7 +55,8 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index e04f9c6faacd3e..8b5c82ce6e6367 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -856,7 +856,9 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
unsigned KillFlag = getKillRegState(KillSrc);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 4efc62fd717c65..854c3694ceba76 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -174,7 +174,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// large registers. See for example the ARM target.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
/// Store the specified register of the given register class to the specified
/// stack frame index. The store instruction is to be added to the given
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index b8a37435f5a64b..f7ff63bb5784eb 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -35,8 +35,8 @@ void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
const DebugLoc &DL,
MCRegister DestinationRegister,
- MCRegister SourceRegister,
- bool KillSource) const {
+ MCRegister SourceRegister, bool KillSource,
+ bool RenamableDest, bool RenamableSrc) const {
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
llvm_unreachable("Impossible reg-to-reg copy");
}
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index 8ad2b9237c9284..2630464f0a76f8 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -49,7 +49,9 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
const DebugLoc &DL, MCRegister DestinationRegister,
- ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/91179
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