[llvm] [RISCV] Optimize pattern `(setcc (selectLT (vfirst_vl ...) , 0, EVL, ...), EVL)` (PR #90538)

[Craig Topper via llvm-commits]

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@@ -13678,9 +13687,92 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   EVT VT = N->getValueType(0);
   EVT OpVT = N0.getValueType();
+  SDLoc DL(N);
+
+  // Both rules are looking for an equality compare.
+  if (!isIntEqualitySetCC(Cond))
+    return SDValue();
+
+  // Rule 1
+  using namespace SDPatternMatch;
+  auto matchSelectCC = [](SDValue Op, SDValue VLCandidate, bool Inverse,
+                          SDValue &Select) -> bool {
+    // It's almost certain the VL which this pattern tries to match
+    // (the EVL parameter from VP intrinsics and the value setcc compares
+    // against) is zext from i32.
+    auto ZExtVL = m_And(m_Value(), m_SpecificInt(APInt::getLowBitsSet(64, 32)));
+
+    // Remove any sext or zext
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topperc wrote:

I'm nervous about peeking through zext and sexts without checking of types. I think we need to know that the compare is only using the same bits from EVL that the vfirst was using.

https://github.com/llvm/llvm-project/pull/90538